1298SN/A/* 29659SAndreas.Sandberg@ARM.com * Copyright (c) 2012 ARM Limited 39659SAndreas.Sandberg@ARM.com * All rights reserved 49659SAndreas.Sandberg@ARM.com * 59659SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69659SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79659SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89659SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99659SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109659SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119659SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129659SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139659SAndreas.Sandberg@ARM.com * 142188SN/A * Copyright (c) 2003-2006 The Regents of The University of Michigan 15298SN/A * All rights reserved. 16298SN/A * 17298SN/A * Redistribution and use in source and binary forms, with or without 18298SN/A * modification, are permitted provided that the following conditions are 19298SN/A * met: redistributions of source code must retain the above copyright 20298SN/A * notice, this list of conditions and the following disclaimer; 21298SN/A * redistributions in binary form must reproduce the above copyright 22298SN/A * notice, this list of conditions and the following disclaimer in the 23298SN/A * documentation and/or other materials provided with the distribution; 24298SN/A * neither the name of the copyright holders nor the names of its 25298SN/A * contributors may be used to endorse or promote products derived from 26298SN/A * this software without specific prior written permission. 27298SN/A * 28298SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29298SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30298SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31298SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32298SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33298SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34298SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35298SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36298SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37298SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38298SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 41298SN/A */ 42298SN/A 438543Sgblack@eecs.umich.edu#ifndef __SIM_PSEUDO_INST_HH__ 448543Sgblack@eecs.umich.edu#define __SIM_PSEUDO_INST_HH__ 458543Sgblack@eecs.umich.edu 462680Sktlim@umich.educlass ThreadContext; 47298SN/A 482980Sgblack@eecs.umich.edu//We need the "Tick" and "Addr" data types from here 496214Snate@binkert.org#include "base/types.hh" 502081SN/A 515504Snate@binkert.orgnamespace PseudoInst { 52349SN/A 539659SAndreas.Sandberg@ARM.com/** 549659SAndreas.Sandberg@ARM.com * Execute a decoded M5 pseudo instruction 559659SAndreas.Sandberg@ARM.com * 569659SAndreas.Sandberg@ARM.com * The ISA-specific code is responsible to decode the pseudo inst 579659SAndreas.Sandberg@ARM.com * function number and subfunction number. After that has been done, 589659SAndreas.Sandberg@ARM.com * the rest of the instruction can be implemented in an ISA-agnostic 599659SAndreas.Sandberg@ARM.com * manner using the ISA-specific getArguments functions. 609659SAndreas.Sandberg@ARM.com * 619659SAndreas.Sandberg@ARM.com * @param func M5 pseudo op major function number (see utility/m5/m5ops.h) 629659SAndreas.Sandberg@ARM.com * @param subfunc M5 minor function number. Mainly used for annotations. 639659SAndreas.Sandberg@ARM.com */ 649659SAndreas.Sandberg@ARM.comuint64_t pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc); 659659SAndreas.Sandberg@ARM.com 665504Snate@binkert.orgvoid arm(ThreadContext *tc); 675504Snate@binkert.orgvoid quiesce(ThreadContext *tc); 688142SAli.Saidi@ARM.comvoid quiesceSkip(ThreadContext *tc); 695504Snate@binkert.orgvoid quiesceNs(ThreadContext *tc, uint64_t ns); 705504Snate@binkert.orgvoid quiesceCycles(ThreadContext *tc, uint64_t cycles); 715504Snate@binkert.orguint64_t quiesceTime(ThreadContext *tc); 725780Ssteve.reinhardt@amd.comuint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, 735780Ssteve.reinhardt@amd.com uint64_t offset); 748734Sdam.sunwoo@arm.comuint64_t writefile(ThreadContext *tc, Addr vaddr, uint64_t len, 758734Sdam.sunwoo@arm.com uint64_t offset, Addr filenameAddr); 765780Ssteve.reinhardt@amd.comvoid loadsymbol(ThreadContext *xc); 775780Ssteve.reinhardt@amd.comvoid addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); 7811289Sgabor.dozsa@arm.comuint64_t initParam(ThreadContext *xc, uint64_t key_str1, uint64_t key_str2); 795741Snate@binkert.orguint64_t rpns(ThreadContext *tc); 805808Snate@binkert.orgvoid wakeCPU(ThreadContext *tc, uint64_t cpuid); 815504Snate@binkert.orgvoid m5exit(ThreadContext *tc, Tick delay); 829457Svilanova@ac.upc.eduvoid m5fail(ThreadContext *tc, Tick delay, uint64_t code); 835504Snate@binkert.orgvoid resetstats(ThreadContext *tc, Tick delay, Tick period); 845504Snate@binkert.orgvoid dumpstats(ThreadContext *tc, Tick delay, Tick period); 855504Snate@binkert.orgvoid dumpresetstats(ThreadContext *tc, Tick delay, Tick period); 865504Snate@binkert.orgvoid m5checkpoint(ThreadContext *tc, Tick delay, Tick period); 875504Snate@binkert.orgvoid debugbreak(ThreadContext *tc); 885504Snate@binkert.orgvoid switchcpu(ThreadContext *tc); 897914SBrad.Beckmann@amd.comvoid workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid); 907914SBrad.Beckmann@amd.comvoid workend(ThreadContext *tc, uint64_t workid, uint64_t threadid); 9111703Smichael.lebeane@amd.comvoid togglesync(ThreadContext *tc); 925504Snate@binkert.org 937811Ssteve.reinhardt@amd.com} // namespace PseudoInst 948543Sgblack@eecs.umich.edu 958543Sgblack@eecs.umich.edu#endif // __SIM_PSEUDO_INST_HH__ 96