arch/arm/tlb.cc

570     Addr vaddr = 0;
572         vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
574         vaddr = vaddr_tainted;
583             if (vaddr & mask(flags & AlignmentMask)) {
597     if (!p->pTable->translate(vaddr, paddr))
613     Addr vaddr = req->getVaddr(); // 32-bit don't have to purify
630             vaddr, te->domain, is_write,
639             if (vaddr & mask(flags & AlignmentMask)) {
642                     vaddr, TlbEntry::DomainType::NoAccess, is_write,
655                 vaddr, ArmFault::PrefetchUncacheable,
668                 // Use PC value instead of vaddr because vaddr might
677                     vaddr, te->domain, is_write,
763         // Use PC value instead of vaddr because vaddr might be aligned to
774             vaddr, te->domain, is_write,
798     Addr vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
825             if (vaddr & mask(flags & AlignmentMask)) {
994             // Use PC value instead of vaddr because vaddr might be aligned to
1046     Addr vaddr = 0;
1048         vaddr = purifyTaggedAddr(vaddr_tainted, tc, aarch64EL, ttbcr);
1050         vaddr = vaddr_tainted;
1078             if (vaddr & mask(flags & AlignmentMask)) {
1092         req->setPaddr(vaddr);
1167         Addr pa = te->pAddr(vaddr);
1173         if ((!is_fetch) && (vaddr & mask(flags & AlignmentMask)) &&
1465     Addr vaddr = 0;
1468         vaddr = purifyTaggedAddr(vaddr_tainted, tc, target_el, ttbcr);
1470         vaddr = vaddr_tainted;
1472     *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el);
1503         *te = lookup(vaddr, asid, vmid, isHyp, is_secure, false, false, target_el);