Searched refs:system (Results 251 - 275 of 289) sorted by relevance

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/gem5/src/cpu/
H A Dbase.hh67 #include "sim/system.hh"
124 * in the system. This is usually used to bucket cpu cores under single DVFS
138 * of the OS process ID) to each request so components in the memory system
150 /** Cache the cache line size that we get from the system */
274 /** Invalid or unknown Pid. Possible when operating system is not present
370 * Verify that the system is in a memory mode supported by the
373 * Implementations are expected to query the system for the
400 System *system; variable
403 * Get the cache line size of the system.
H A Dsimple_thread.hh69 #include "sim/system.hh"
87 * in full system mode. For CPU models that do not need more advanced
129 System *system; member in class:SimpleThread
210 System *getSystemPtr() override { return system; }
/gem5/ext/googletest/googlemock/scripts/generator/cpp/
H A Dast.py156 def __init__(self, start, end, filename, system):
159 self.system = system
163 if self.system:
829 system = name[0] == '<'
831 return Include(token.start, token.end, filename, system)
/gem5/src/sim/
H A Dpseudo_inst.cc80 #include "sim/system.hh"
327 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
422 val = tc->getCpuPtr()->system->init_param;
H A Dsystem.cc48 #include "sim/system.hh"
115 instEventQueue("system instruction-based event queue"),
119 // add self to global system list
139 // Get the generic system master IDs
150 inform("No kernel set for full system simulation. "
186 // Loading only needs to happen once and after memory system is
202 // Set back pointers to the system in all memories
204 params()->memories[x]->system(this);
219 // check that the system port is connected
427 // also serialize the memories in the system
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H A Dsyscall_emul.hh329 /// Futex system call
358 // Ensure futex system call accessed atomically.
365 * (a different thread must have changed it before the system call was
385 // Ensure futex system call accessed atomically.
870 * Return the host's error code back through the system call to the
880 { "/proc/meminfo/", "/system/", "/platform/", "/etc/passwd" };
1019 sysinfo->totalram = process->system->memSize();
1527 DPRINTF_SYSCALL(Verbose, "clone: no spare thread context in system"
1541 pp->system = p->system;
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/gem5/src/gpu-compute/
H A Ddispatcher.cc52 : DmaDevice(p), _masterId(p->system->getMasterId(this, "disp")),
/gem5/src/arch/x86/
H A Dsystem.cc42 #include "arch/x86/system.hh"
80 attr.system = desc.s;
156 initDesc.s = 1; // system segment
/gem5/src/cpu/o3/
H A Dthread_context.hh118 /** Returns a pointer to the system. */
119 System *getSystemPtr() override { return cpu->system; }
H A Dcpu.hh182 /** Check if a system is in a drained state. */
672 /** Gets a free thread id. Use if thread ids change across system. */
692 /** Pointer to the system. */
693 System *system; member in class:FullO3CPU
707 /** Mapping for system thread id to cpu id */
/gem5/src/cpu/minor/
H A Dexecute.cc453 /* Set to true if the mem op. is issued and sent to the mem system */
844 cpu.system->pcEventQueue.service(thread);
864 * thread and system */
870 cpu.system->totalNumInsts++;
874 cpu.system->instEventQueue.serviceEvents(cpu.system->totalNumInsts);
1040 * (committed, discarded, issued to the memory system)
1238 * and 'issued' into the memory system so we need to
/gem5/src/mem/ruby/slicc_interface/
H A DAbstractController.cc46 #include "mem/ruby/system/GPUCoalescer.hh"
47 #include "mem/ruby/system/RubySystem.hh"
48 #include "mem/ruby/system/Sequencer.hh"
49 #include "sim/system.hh"
54 m_masterId(p->system->getMasterId(this)), m_is_blocking(false),
/gem5/src/learning_gem5/part2/
H A Dsimple_cache.cc35 #include "sim/system.hh"
40 blockSize(params->system->cacheLineSize()),
/gem5/src/dev/arm/
H A DRealView.py269 system = Param.System(Parent.any, "system") variable in class:RealViewTemperatureSensor
400 system = Param.ArmSystem(Parent.any, "system") variable in class:GenericTimer
471 enable_capture = Param.Bool(True, "capture frame to system.framebuffer.bmp")
484 "system.framebuffer.{extension}")
542 system = Param.System(Parent.any, "system") variable in class:RealView
938 0x1c010000-0x1c01ffff: realview_io (VE system control regs.)
1086 # system
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H A Dsmmu_v3_transl.cc46 #include "sim/system.hh"
119 assert(smmu.system.isTimingMode());
1207 if (!smmu.system.isTimingMode())
1252 if (smmu.system.isAtomicMode()) {
1254 } else if (smmu.system.isTimingMode()) {
/gem5/ext/systemc/src/
H A Dsystemc.h157 using std::system;
329 // the constructor for the system's union wait on Unix and Linux. This
/gem5/src/dev/virtio/
H A Dfs9p.cc62 #include "sim/system.hh"
121 queue(params->system->physProxy, params->queueSize, *this)
/gem5/configs/example/
H A Dfs.py106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
108 # Set the cache line size for the entire system
114 # Create a source clock for the system and set the clock period
129 print("Error: a kernel must be provided to run in full system mode")
165 # Tie the cpu ports to the correct ruby system ports
185 # By default the IOCache runs at the system clock
234 # driver system CPU is always simple, so is the memory
258 # Create a source clock for the system and set the clock period
278 print("Error: a kernel must be provided to run in full system mode")
315 # system unde
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/gem5/src/dev/sparc/
H A Diob.cc54 #include "sim/system.hh"
63 assert (params()->system->threadContexts.size() <= MaxNiagaraProcs);
/gem5/src/mem/cache/prefetch/
H A Dqueued.cc442 dpp.tc = cache->system->getThreadContext(translation_req->contextId());
/gem5/src/mem/cache/
H A Dcache.cc75 : BaseCache(p, p->system->cacheLineSize()),
423 // copies in the system; go out and invalidate them all
448 // other caches in the system know that the another cache
457 // every cache in the system
471 // section above to ensure all other copies in the system are
778 assert(tgt_pkt->req->masterId() < system->maxMasters());
/gem5/src/cpu/trace/
H A Dtrace_cpu.cc53 instMasterID(params->system->getMasterId(this, "inst")),
54 dataMasterID(params->system->getMasterId(this, "data")),
146 // CPUs in the system. If not then instantiate a counted event.
/gem5/src/cpu/simple/
H A Dtiming.cc61 #include "sim/system.hh"
154 system->totalNumInsts = 0;
202 if (!system->isTimingMode()) {
203 fatal("The timing CPU requires the memory system to be in "
281 // memory system takes ownership of packet
490 // memory system takes ownership of packet
713 // ownership of packet transferred to memory system
982 // memory system (fetch and load/store) to set the pace.
1036 // memory system takes ownership of packet
1042 // memory system take
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/gem5/src/mem/
H A Ddram_ctrl.cc57 #include "sim/system.hh"
131 // if actual DRAM size does not match memory capacity in system warn!
200 // ensure that the system pointer is initialised
214 // if the system uses a channel striping granularity that
224 if (system()->cacheLineSize() > range.granularity()) {
243 // remember the memory system mode of operation
244 isTimingMode = system()->isTimingMode();
733 // we have now serviced all children packets of a system packet
2679 .desc("Total read bytes from the system interface side");
2683 .desc("Total written bytes from the system interfac
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/gem5/src/arch/x86/regs/
H A Dmisc.hh48 //These get defined in some system headers (at least termbits.h). That confuses
805 Bitfield<17> os; // Operating-system mode
999 Bitfield<15> system; member in namespace:X86ISA

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