14104Ssaidi@eecs.umich.edu/* 24104Ssaidi@eecs.umich.edu * Copyright (c) 2006 The Regents of The University of Michigan 34104Ssaidi@eecs.umich.edu * All rights reserved. 44104Ssaidi@eecs.umich.edu * 54104Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64104Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74104Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94104Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104104Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114104Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124104Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134104Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144104Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154104Ssaidi@eecs.umich.edu * 164104Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174104Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184104Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194104Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204104Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214104Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224104Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234104Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244104Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254104Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264104Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274104Ssaidi@eecs.umich.edu * 284104Ssaidi@eecs.umich.edu * Authors: Ali Saidi 294104Ssaidi@eecs.umich.edu */ 304104Ssaidi@eecs.umich.edu 314104Ssaidi@eecs.umich.edu/** @file 324104Ssaidi@eecs.umich.edu * This device implemetns the niagara I/O bridge chip. It manages incomming 334104Ssaidi@eecs.umich.edu * interrupts and posts them to the CPU when needed. It holds mask registers and 344104Ssaidi@eecs.umich.edu * various status registers for CPUs to check what interrupts are pending as 354104Ssaidi@eecs.umich.edu * well as facilities to send IPIs to other cpus. 364104Ssaidi@eecs.umich.edu */ 374104Ssaidi@eecs.umich.edu 3811793Sbrandon.potter@amd.com#include "dev/sparc/iob.hh" 3911793Sbrandon.potter@amd.com 404104Ssaidi@eecs.umich.edu#include <cstring> 414104Ssaidi@eecs.umich.edu 428229Snate@binkert.org#include "arch/sparc/faults.hh" 4313912Sgabeblack@google.com#include "arch/sparc/interrupts.hh" 444104Ssaidi@eecs.umich.edu#include "arch/sparc/isa_traits.hh" 457723SAli.Saidi@ARM.com#include "base/bitfield.hh" 464104Ssaidi@eecs.umich.edu#include "base/trace.hh" 474104Ssaidi@eecs.umich.edu#include "cpu/intr_control.hh" 488739Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 498232Snate@binkert.org#include "debug/Iob.hh" 504104Ssaidi@eecs.umich.edu#include "dev/platform.hh" 518229Snate@binkert.org#include "mem/packet_access.hh" 524104Ssaidi@eecs.umich.edu#include "mem/port.hh" 534194Ssaidi@eecs.umich.edu#include "sim/faults.hh" 544104Ssaidi@eecs.umich.edu#include "sim/system.hh" 554104Ssaidi@eecs.umich.edu 564762Snate@binkert.orgIob::Iob(const Params *p) 574104Ssaidi@eecs.umich.edu : PioDevice(p), ic(p->platform->intrctrl) 584104Ssaidi@eecs.umich.edu{ 594104Ssaidi@eecs.umich.edu iobManAddr = ULL(0x9800000000); 604104Ssaidi@eecs.umich.edu iobManSize = ULL(0x0100000000); 614104Ssaidi@eecs.umich.edu iobJBusAddr = ULL(0x9F00000000); 624104Ssaidi@eecs.umich.edu iobJBusSize = ULL(0x0100000000); 634104Ssaidi@eecs.umich.edu assert (params()->system->threadContexts.size() <= MaxNiagaraProcs); 645103Ssaidi@eecs.umich.edu 655103Ssaidi@eecs.umich.edu pioDelay = p->pio_latency; 665103Ssaidi@eecs.umich.edu 674104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; ++x) { 684104Ssaidi@eecs.umich.edu intMan[x].cpu = 0; 694104Ssaidi@eecs.umich.edu intMan[x].vector = 0; 704104Ssaidi@eecs.umich.edu intCtl[x].mask = true; 714104Ssaidi@eecs.umich.edu intCtl[x].pend = false; 724104Ssaidi@eecs.umich.edu } 734104Ssaidi@eecs.umich.edu 744104Ssaidi@eecs.umich.edu} 754104Ssaidi@eecs.umich.edu 764104Ssaidi@eecs.umich.eduTick 774104Ssaidi@eecs.umich.eduIob::read(PacketPtr pkt) 784104Ssaidi@eecs.umich.edu{ 794104Ssaidi@eecs.umich.edu 804104Ssaidi@eecs.umich.edu if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 814104Ssaidi@eecs.umich.edu readIob(pkt); 824104Ssaidi@eecs.umich.edu else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 834104Ssaidi@eecs.umich.edu readJBus(pkt); 844104Ssaidi@eecs.umich.edu else 854104Ssaidi@eecs.umich.edu panic("Invalid address reached Iob\n"); 864104Ssaidi@eecs.umich.edu 874870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 884104Ssaidi@eecs.umich.edu return pioDelay; 894104Ssaidi@eecs.umich.edu} 904104Ssaidi@eecs.umich.edu 914104Ssaidi@eecs.umich.eduvoid 924104Ssaidi@eecs.umich.eduIob::readIob(PacketPtr pkt) 934104Ssaidi@eecs.umich.edu{ 944104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobManAddr; 954104Ssaidi@eecs.umich.edu 9611294Sandreas.hansson@arm.com assert(IntManAddr == 0); 9711294Sandreas.hansson@arm.com if (accessAddr < IntManAddr + IntManSize) { 986712Snate@binkert.org int index = (accessAddr - IntManAddr) >> 3; 996712Snate@binkert.org uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0; 10013231Sgabeblack@google.com pkt->setBE(data); 1014104Ssaidi@eecs.umich.edu return; 1024104Ssaidi@eecs.umich.edu } 1034104Ssaidi@eecs.umich.edu 1044104Ssaidi@eecs.umich.edu if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 1056712Snate@binkert.org int index = (accessAddr - IntCtlAddr) >> 3; 1066712Snate@binkert.org uint64_t data = intCtl[index].mask ? 1 << 2 : 0 | 1076712Snate@binkert.org intCtl[index].pend ? 1 << 0 : 0; 10813231Sgabeblack@google.com pkt->setBE(data); 1094104Ssaidi@eecs.umich.edu return; 1104104Ssaidi@eecs.umich.edu } 1114104Ssaidi@eecs.umich.edu 1124104Ssaidi@eecs.umich.edu if (accessAddr == JIntVecAddr) { 11313231Sgabeblack@google.com pkt->setBE(jIntVec); 1144104Ssaidi@eecs.umich.edu return; 1154104Ssaidi@eecs.umich.edu } 1164104Ssaidi@eecs.umich.edu 1174104Ssaidi@eecs.umich.edu panic("Read to unknown IOB offset 0x%x\n", accessAddr); 1184104Ssaidi@eecs.umich.edu} 1194104Ssaidi@eecs.umich.edu 1204104Ssaidi@eecs.umich.eduvoid 1214104Ssaidi@eecs.umich.eduIob::readJBus(PacketPtr pkt) 1224104Ssaidi@eecs.umich.edu{ 1234104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobJBusAddr; 12411005Sandreas.sandberg@arm.com ContextID cpuid = pkt->req->contextId(); 1254104Ssaidi@eecs.umich.edu int index; 1264104Ssaidi@eecs.umich.edu uint64_t data; 1274104Ssaidi@eecs.umich.edu 1284104Ssaidi@eecs.umich.edu 1294104Ssaidi@eecs.umich.edu 1304104Ssaidi@eecs.umich.edu 1314104Ssaidi@eecs.umich.edu if (accessAddr >= JIntData0Addr && accessAddr < JIntData1Addr) { 1324104Ssaidi@eecs.umich.edu index = (accessAddr - JIntData0Addr) >> 3; 13313231Sgabeblack@google.com pkt->setBE(jBusData0[index]); 1344104Ssaidi@eecs.umich.edu return; 1354104Ssaidi@eecs.umich.edu } 1364104Ssaidi@eecs.umich.edu 1374104Ssaidi@eecs.umich.edu if (accessAddr >= JIntData1Addr && accessAddr < JIntDataA0Addr) { 1384104Ssaidi@eecs.umich.edu index = (accessAddr - JIntData1Addr) >> 3; 13913231Sgabeblack@google.com pkt->setBE(jBusData1[index]); 1404104Ssaidi@eecs.umich.edu return; 1414104Ssaidi@eecs.umich.edu } 1424104Ssaidi@eecs.umich.edu 1434104Ssaidi@eecs.umich.edu if (accessAddr == JIntDataA0Addr) { 14413231Sgabeblack@google.com pkt->setBE(jBusData0[cpuid]); 1454104Ssaidi@eecs.umich.edu return; 1464104Ssaidi@eecs.umich.edu } 1474104Ssaidi@eecs.umich.edu 1484104Ssaidi@eecs.umich.edu if (accessAddr == JIntDataA1Addr) { 14913231Sgabeblack@google.com pkt->setBE(jBusData1[cpuid]); 1504104Ssaidi@eecs.umich.edu return; 1514104Ssaidi@eecs.umich.edu } 1524104Ssaidi@eecs.umich.edu 1534104Ssaidi@eecs.umich.edu if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 1544104Ssaidi@eecs.umich.edu index = (accessAddr - JIntBusyAddr) >> 3; 1554104Ssaidi@eecs.umich.edu data = jIntBusy[index].busy ? 1 << 5 : 0 | 1564104Ssaidi@eecs.umich.edu jIntBusy[index].source; 15713231Sgabeblack@google.com pkt->setBE(data); 1584104Ssaidi@eecs.umich.edu return; 1594104Ssaidi@eecs.umich.edu } 1604104Ssaidi@eecs.umich.edu if (accessAddr == JIntABusyAddr) { 1614104Ssaidi@eecs.umich.edu data = jIntBusy[cpuid].busy ? 1 << 5 : 0 | 1624104Ssaidi@eecs.umich.edu jIntBusy[cpuid].source; 16313231Sgabeblack@google.com pkt->setBE(data); 1644104Ssaidi@eecs.umich.edu return; 1654104Ssaidi@eecs.umich.edu }; 1664104Ssaidi@eecs.umich.edu 1674104Ssaidi@eecs.umich.edu panic("Read to unknown JBus offset 0x%x\n", accessAddr); 1684104Ssaidi@eecs.umich.edu} 1694104Ssaidi@eecs.umich.edu 1704104Ssaidi@eecs.umich.eduTick 1714104Ssaidi@eecs.umich.eduIob::write(PacketPtr pkt) 1724104Ssaidi@eecs.umich.edu{ 1734104Ssaidi@eecs.umich.edu if (pkt->getAddr() >= iobManAddr && pkt->getAddr() < iobManAddr + iobManSize) 1744104Ssaidi@eecs.umich.edu writeIob(pkt); 1754104Ssaidi@eecs.umich.edu else if (pkt->getAddr() >= iobJBusAddr && pkt->getAddr() < iobJBusAddr+iobJBusSize) 1764104Ssaidi@eecs.umich.edu writeJBus(pkt); 1774104Ssaidi@eecs.umich.edu else 1784104Ssaidi@eecs.umich.edu panic("Invalid address reached Iob\n"); 1794104Ssaidi@eecs.umich.edu 1804104Ssaidi@eecs.umich.edu 1814870Sstever@eecs.umich.edu pkt->makeAtomicResponse(); 1824104Ssaidi@eecs.umich.edu return pioDelay; 1834104Ssaidi@eecs.umich.edu} 1844104Ssaidi@eecs.umich.edu 1854104Ssaidi@eecs.umich.eduvoid 1864104Ssaidi@eecs.umich.eduIob::writeIob(PacketPtr pkt) 1874104Ssaidi@eecs.umich.edu{ 1884104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobManAddr; 1894104Ssaidi@eecs.umich.edu int index; 1904104Ssaidi@eecs.umich.edu uint64_t data; 1914104Ssaidi@eecs.umich.edu 19211294Sandreas.hansson@arm.com assert(IntManAddr == 0); 19311294Sandreas.hansson@arm.com if (accessAddr < IntManAddr + IntManSize) { 1944104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 19513231Sgabeblack@google.com data = pkt->getBE<uint64_t>(); 1964104Ssaidi@eecs.umich.edu intMan[index].cpu = bits(data,12,8); 1974104Ssaidi@eecs.umich.edu intMan[index].vector = bits(data,5,0); 1984216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote IntMan %d cpu %d, vec %d\n", index, 1994216Ssaidi@eecs.umich.edu intMan[index].cpu, intMan[index].vector); 2004104Ssaidi@eecs.umich.edu return; 2014104Ssaidi@eecs.umich.edu } 2024104Ssaidi@eecs.umich.edu 2034104Ssaidi@eecs.umich.edu if (accessAddr >= IntCtlAddr && accessAddr < IntCtlAddr + IntCtlSize) { 2046712Snate@binkert.org index = (accessAddr - IntCtlAddr) >> 3; 20513231Sgabeblack@google.com data = pkt->getBE<uint64_t>(); 2064104Ssaidi@eecs.umich.edu intCtl[index].mask = bits(data,2,2); 2074104Ssaidi@eecs.umich.edu if (bits(data,1,1)) 2084104Ssaidi@eecs.umich.edu intCtl[index].pend = false; 2094216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote IntCtl %d pend %d cleared %d\n", index, 2104216Ssaidi@eecs.umich.edu intCtl[index].pend, bits(data,2,2)); 2114104Ssaidi@eecs.umich.edu return; 2124104Ssaidi@eecs.umich.edu } 2134104Ssaidi@eecs.umich.edu 2144104Ssaidi@eecs.umich.edu if (accessAddr == JIntVecAddr) { 21513231Sgabeblack@google.com jIntVec = bits(pkt->getBE<uint64_t>(), 5,0); 2164216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote jIntVec %d\n", jIntVec); 2174104Ssaidi@eecs.umich.edu return; 2184104Ssaidi@eecs.umich.edu } 2194104Ssaidi@eecs.umich.edu 2204104Ssaidi@eecs.umich.edu if (accessAddr >= IntVecDisAddr && accessAddr < IntVecDisAddr + IntVecDisSize) { 2214104Ssaidi@eecs.umich.edu Type type; 2224104Ssaidi@eecs.umich.edu int cpu_id; 2234104Ssaidi@eecs.umich.edu int vector; 2244104Ssaidi@eecs.umich.edu index = (accessAddr - IntManAddr) >> 3; 22513231Sgabeblack@google.com data = pkt->getBE<uint64_t>(); 2264104Ssaidi@eecs.umich.edu type = (Type)bits(data,17,16); 2274104Ssaidi@eecs.umich.edu cpu_id = bits(data, 12,8); 2284104Ssaidi@eecs.umich.edu vector = bits(data,5,0); 2294104Ssaidi@eecs.umich.edu generateIpi(type,cpu_id, vector); 2304104Ssaidi@eecs.umich.edu return; 2314104Ssaidi@eecs.umich.edu } 2324104Ssaidi@eecs.umich.edu 2334104Ssaidi@eecs.umich.edu panic("Write to unknown IOB offset 0x%x\n", accessAddr); 2344104Ssaidi@eecs.umich.edu} 2354104Ssaidi@eecs.umich.edu 2364104Ssaidi@eecs.umich.eduvoid 2374104Ssaidi@eecs.umich.eduIob::writeJBus(PacketPtr pkt) 2384104Ssaidi@eecs.umich.edu{ 2394104Ssaidi@eecs.umich.edu Addr accessAddr = pkt->getAddr() - iobJBusAddr; 24011005Sandreas.sandberg@arm.com ContextID cpuid = pkt->req->contextId(); 2414104Ssaidi@eecs.umich.edu int index; 2424104Ssaidi@eecs.umich.edu uint64_t data; 2434104Ssaidi@eecs.umich.edu 2444104Ssaidi@eecs.umich.edu if (accessAddr >= JIntBusyAddr && accessAddr < JIntBusyAddr + JIntBusySize) { 2454104Ssaidi@eecs.umich.edu index = (accessAddr - JIntBusyAddr) >> 3; 24613231Sgabeblack@google.com data = pkt->getBE<uint64_t>(); 2474104Ssaidi@eecs.umich.edu jIntBusy[index].busy = bits(data,5,5); 2484216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", index, 2494216Ssaidi@eecs.umich.edu jIntBusy[index].busy); 2504104Ssaidi@eecs.umich.edu return; 2514104Ssaidi@eecs.umich.edu } 2524104Ssaidi@eecs.umich.edu if (accessAddr == JIntABusyAddr) { 25313231Sgabeblack@google.com data = pkt->getBE<uint64_t>(); 2544104Ssaidi@eecs.umich.edu jIntBusy[cpuid].busy = bits(data,5,5); 2554216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Wrote jIntBusy index %d busy: %d\n", cpuid, 2564216Ssaidi@eecs.umich.edu jIntBusy[cpuid].busy); 2574104Ssaidi@eecs.umich.edu return; 2584104Ssaidi@eecs.umich.edu }; 2594104Ssaidi@eecs.umich.edu 2604104Ssaidi@eecs.umich.edu panic("Write to unknown JBus offset 0x%x\n", accessAddr); 2614104Ssaidi@eecs.umich.edu} 2624104Ssaidi@eecs.umich.edu 2634104Ssaidi@eecs.umich.eduvoid 2644104Ssaidi@eecs.umich.eduIob::receiveDeviceInterrupt(DeviceId devid) 2654104Ssaidi@eecs.umich.edu{ 2664104Ssaidi@eecs.umich.edu assert(devid < NumDeviceIds); 2674104Ssaidi@eecs.umich.edu if (intCtl[devid].mask) 2684104Ssaidi@eecs.umich.edu return; 2694104Ssaidi@eecs.umich.edu intCtl[devid].mask = true; 2704104Ssaidi@eecs.umich.edu intCtl[devid].pend = true; 2714216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Receiving Device interrupt: %d for cpu %d vec %d\n", 2724216Ssaidi@eecs.umich.edu devid, intMan[devid].cpu, intMan[devid].vector); 2734104Ssaidi@eecs.umich.edu ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector); 2744104Ssaidi@eecs.umich.edu} 2754104Ssaidi@eecs.umich.edu 2764104Ssaidi@eecs.umich.edu 2774104Ssaidi@eecs.umich.eduvoid 2784104Ssaidi@eecs.umich.eduIob::generateIpi(Type type, int cpu_id, int vector) 2794104Ssaidi@eecs.umich.edu{ 2804194Ssaidi@eecs.umich.edu SparcISA::SparcFault<SparcISA::PowerOnReset> *por = new SparcISA::PowerOnReset(); 2815719Shsul@eecs.umich.edu if (cpu_id >= sys->numContexts()) 2824104Ssaidi@eecs.umich.edu return; 2834130Ssaidi@eecs.umich.edu 2844194Ssaidi@eecs.umich.edu switch (type) { 2854194Ssaidi@eecs.umich.edu case 0: // interrupt 2864216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Generating interrupt because of I/O write to cpu: %d vec %d\n", 2874216Ssaidi@eecs.umich.edu cpu_id, vector); 2884194Ssaidi@eecs.umich.edu ic->post(cpu_id, SparcISA::IT_INT_VEC, vector); 2894194Ssaidi@eecs.umich.edu break; 2904194Ssaidi@eecs.umich.edu case 1: // reset 2914194Ssaidi@eecs.umich.edu warn("Sending reset to CPU: %d\n", cpu_id); 2924194Ssaidi@eecs.umich.edu if (vector != por->trapType()) 2934194Ssaidi@eecs.umich.edu panic("Don't know how to set non-POR reset to cpu\n"); 2944194Ssaidi@eecs.umich.edu por->invoke(sys->threadContexts[cpu_id]); 2954194Ssaidi@eecs.umich.edu sys->threadContexts[cpu_id]->activate(); 2964194Ssaidi@eecs.umich.edu break; 2974194Ssaidi@eecs.umich.edu case 2: // idle -- this means stop executing and don't wake on interrupts 2984216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Idling CPU because of I/O write cpu: %d\n", cpu_id); 2994194Ssaidi@eecs.umich.edu sys->threadContexts[cpu_id]->halt(); 3004194Ssaidi@eecs.umich.edu break; 3014194Ssaidi@eecs.umich.edu case 3: // resume 3024216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Resuming CPU because of I/O write cpu: %d\n", cpu_id); 3034194Ssaidi@eecs.umich.edu sys->threadContexts[cpu_id]->activate(); 3044194Ssaidi@eecs.umich.edu break; 3054194Ssaidi@eecs.umich.edu default: 3064194Ssaidi@eecs.umich.edu panic("Invalid type to generate ipi\n"); 3074194Ssaidi@eecs.umich.edu } 3084104Ssaidi@eecs.umich.edu} 3094104Ssaidi@eecs.umich.edu 3104104Ssaidi@eecs.umich.edubool 3114104Ssaidi@eecs.umich.eduIob::receiveJBusInterrupt(int cpu_id, int source, uint64_t d0, uint64_t d1) 3124104Ssaidi@eecs.umich.edu{ 3134104Ssaidi@eecs.umich.edu // If we are already dealing with an interrupt for that cpu we can't deal 3144104Ssaidi@eecs.umich.edu // with another one right now... come back later 3154104Ssaidi@eecs.umich.edu if (jIntBusy[cpu_id].busy) 3164104Ssaidi@eecs.umich.edu return false; 3174104Ssaidi@eecs.umich.edu 3184216Ssaidi@eecs.umich.edu DPRINTF(Iob, "Receiving jBus interrupt: %d for cpu %d vec %d\n", 3194216Ssaidi@eecs.umich.edu source, cpu_id, jIntVec); 3204216Ssaidi@eecs.umich.edu 3214104Ssaidi@eecs.umich.edu jIntBusy[cpu_id].busy = true; 3224104Ssaidi@eecs.umich.edu jIntBusy[cpu_id].source = source; 3234104Ssaidi@eecs.umich.edu jBusData0[cpu_id] = d0; 3244104Ssaidi@eecs.umich.edu jBusData1[cpu_id] = d1; 3254104Ssaidi@eecs.umich.edu 3264104Ssaidi@eecs.umich.edu ic->post(cpu_id, SparcISA::IT_INT_VEC, jIntVec); 3274104Ssaidi@eecs.umich.edu return true; 3284104Ssaidi@eecs.umich.edu} 3294104Ssaidi@eecs.umich.edu 3308711Sandreas.hansson@arm.comAddrRangeList 3319090Sandreas.hansson@arm.comIob::getAddrRanges() const 3324104Ssaidi@eecs.umich.edu{ 3338711Sandreas.hansson@arm.com AddrRangeList ranges; 3348711Sandreas.hansson@arm.com ranges.push_back(RangeSize(iobManAddr, iobManSize)); 3358711Sandreas.hansson@arm.com ranges.push_back(RangeSize(iobJBusAddr, iobJBusSize)); 3368711Sandreas.hansson@arm.com return ranges; 3374104Ssaidi@eecs.umich.edu} 3384104Ssaidi@eecs.umich.edu 3394104Ssaidi@eecs.umich.edu 3404104Ssaidi@eecs.umich.eduvoid 34110905Sandreas.sandberg@arm.comIob::serialize(CheckpointOut &cp) const 3424104Ssaidi@eecs.umich.edu{ 3434104Ssaidi@eecs.umich.edu 3444104Ssaidi@eecs.umich.edu SERIALIZE_SCALAR(jIntVec); 3454104Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 3464104Ssaidi@eecs.umich.edu SERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 3474104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; x++) { 34810905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("Int%d", x)); 34910905Sandreas.sandberg@arm.com paramOut(cp, "cpu", intMan[x].cpu); 35010905Sandreas.sandberg@arm.com paramOut(cp, "vector", intMan[x].vector); 35110905Sandreas.sandberg@arm.com paramOut(cp, "mask", intCtl[x].mask); 35210905Sandreas.sandberg@arm.com paramOut(cp, "pend", intCtl[x].pend); 3534104Ssaidi@eecs.umich.edu }; 3544104Ssaidi@eecs.umich.edu for (int x = 0; x < MaxNiagaraProcs; x++) { 35510905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("jIntBusy%d", x)); 35610905Sandreas.sandberg@arm.com paramOut(cp, "busy", jIntBusy[x].busy); 35710905Sandreas.sandberg@arm.com paramOut(cp, "source", jIntBusy[x].source); 3584104Ssaidi@eecs.umich.edu }; 3594104Ssaidi@eecs.umich.edu} 3604104Ssaidi@eecs.umich.edu 3614104Ssaidi@eecs.umich.eduvoid 36210905Sandreas.sandberg@arm.comIob::unserialize(CheckpointIn &cp) 3634104Ssaidi@eecs.umich.edu{ 3644104Ssaidi@eecs.umich.edu UNSERIALIZE_SCALAR(jIntVec); 3654104Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(jBusData0, MaxNiagaraProcs); 3664104Ssaidi@eecs.umich.edu UNSERIALIZE_ARRAY(jBusData1, MaxNiagaraProcs); 3674104Ssaidi@eecs.umich.edu for (int x = 0; x < NumDeviceIds; x++) { 36810905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("Int%d", x)); 36910905Sandreas.sandberg@arm.com paramIn(cp, "cpu", intMan[x].cpu); 37010905Sandreas.sandberg@arm.com paramIn(cp, "vector", intMan[x].vector); 37110905Sandreas.sandberg@arm.com paramIn(cp, "mask", intCtl[x].mask); 37210905Sandreas.sandberg@arm.com paramIn(cp, "pend", intCtl[x].pend); 3734104Ssaidi@eecs.umich.edu }; 3744104Ssaidi@eecs.umich.edu for (int x = 0; x < MaxNiagaraProcs; x++) { 37510905Sandreas.sandberg@arm.com ScopedCheckpointSection sec(cp, csprintf("jIntBusy%d", x)); 37610905Sandreas.sandberg@arm.com paramIn(cp, "busy", jIntBusy[x].busy); 37710905Sandreas.sandberg@arm.com paramIn(cp, "source", jIntBusy[x].source); 3784104Ssaidi@eecs.umich.edu }; 3794104Ssaidi@eecs.umich.edu} 3804104Ssaidi@eecs.umich.edu 3814762Snate@binkert.orgIob * 3824762Snate@binkert.orgIobParams::create() 3834104Ssaidi@eecs.umich.edu{ 3844762Snate@binkert.org return new Iob(this); 3854104Ssaidi@eecs.umich.edu} 386