1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_MISCREGS_HH__
41#define __ARCH_X86_MISCREGS_HH__
42
43#include "arch/x86/regs/segment.hh"
44#include "arch/x86/x86_traits.hh"
45#include "base/bitunion.hh"
46#include "base/logging.hh"
47
48//These get defined in some system headers (at least termbits.h). That confuses
49//things here significantly.
50#undef CR0
51#undef CR2
52#undef CR3
53
54namespace X86ISA
55{
56    enum CondFlagBit {
57        CFBit = 1 << 0,
58        PFBit = 1 << 2,
59        ECFBit = 1 << 3,
60        AFBit = 1 << 4,
61        EZFBit = 1 << 5,
62        ZFBit = 1 << 6,
63        SFBit = 1 << 7,
64        DFBit = 1 << 10,
65        OFBit = 1 << 11
66    };
67
68    const uint32_t cfofMask = CFBit | OFBit;
69    const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit;
70
71    enum RFLAGBit {
72        TFBit = 1 << 8,
73        IFBit = 1 << 9,
74        NTBit = 1 << 14,
75        RFBit = 1 << 16,
76        VMBit = 1 << 17,
77        ACBit = 1 << 18,
78        VIFBit = 1 << 19,
79        VIPBit = 1 << 20,
80        IDBit = 1 << 21
81    };
82
83    enum X87StatusBit {
84        // Exception Flags
85        IEBit = 1 << 0,
86        DEBit = 1 << 1,
87        ZEBit = 1 << 2,
88        OEBit = 1 << 3,
89        UEBit = 1 << 4,
90        PEBit = 1 << 5,
91
92        // !Exception Flags
93        StackFaultBit = 1 << 6,
94        ErrSummaryBit = 1 << 7,
95        CC0Bit = 1 << 8,
96        CC1Bit = 1 << 9,
97        CC2Bit = 1 << 10,
98        CC3Bit = 1 << 14,
99        BusyBit = 1 << 15,
100    };
101
102    enum MiscRegIndex
103    {
104        // Control registers
105        // Most of these are invalid.  See isValidMiscReg() below.
106        MISCREG_CR_BASE,
107        MISCREG_CR0 = MISCREG_CR_BASE,
108        MISCREG_CR1,
109        MISCREG_CR2,
110        MISCREG_CR3,
111        MISCREG_CR4,
112        MISCREG_CR5,
113        MISCREG_CR6,
114        MISCREG_CR7,
115        MISCREG_CR8,
116        MISCREG_CR9,
117        MISCREG_CR10,
118        MISCREG_CR11,
119        MISCREG_CR12,
120        MISCREG_CR13,
121        MISCREG_CR14,
122        MISCREG_CR15,
123
124        // Debug registers
125        MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
126        MISCREG_DR0 = MISCREG_DR_BASE,
127        MISCREG_DR1,
128        MISCREG_DR2,
129        MISCREG_DR3,
130        MISCREG_DR4,
131        MISCREG_DR5,
132        MISCREG_DR6,
133        MISCREG_DR7,
134
135        // Flags register
136        MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
137
138        //Register to keep handy values like the CPU mode in.
139        MISCREG_M5_REG,
140
141        /*
142         * Model Specific Registers
143         */
144        // Time stamp counter
145        MISCREG_TSC,
146
147        MISCREG_MTRRCAP,
148
149        MISCREG_SYSENTER_CS,
150        MISCREG_SYSENTER_ESP,
151        MISCREG_SYSENTER_EIP,
152
153        MISCREG_MCG_CAP,
154        MISCREG_MCG_STATUS,
155        MISCREG_MCG_CTL,
156
157        MISCREG_DEBUG_CTL_MSR,
158
159        MISCREG_LAST_BRANCH_FROM_IP,
160        MISCREG_LAST_BRANCH_TO_IP,
161        MISCREG_LAST_EXCEPTION_FROM_IP,
162        MISCREG_LAST_EXCEPTION_TO_IP,
163
164        MISCREG_MTRR_PHYS_BASE_BASE,
165        MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
166        MISCREG_MTRR_PHYS_BASE_1,
167        MISCREG_MTRR_PHYS_BASE_2,
168        MISCREG_MTRR_PHYS_BASE_3,
169        MISCREG_MTRR_PHYS_BASE_4,
170        MISCREG_MTRR_PHYS_BASE_5,
171        MISCREG_MTRR_PHYS_BASE_6,
172        MISCREG_MTRR_PHYS_BASE_7,
173        MISCREG_MTRR_PHYS_BASE_END,
174
175        MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END,
176        MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
177        MISCREG_MTRR_PHYS_MASK_1,
178        MISCREG_MTRR_PHYS_MASK_2,
179        MISCREG_MTRR_PHYS_MASK_3,
180        MISCREG_MTRR_PHYS_MASK_4,
181        MISCREG_MTRR_PHYS_MASK_5,
182        MISCREG_MTRR_PHYS_MASK_6,
183        MISCREG_MTRR_PHYS_MASK_7,
184        MISCREG_MTRR_PHYS_MASK_END,
185
186        MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END,
187        MISCREG_MTRR_FIX_16K_80000,
188        MISCREG_MTRR_FIX_16K_A0000,
189        MISCREG_MTRR_FIX_4K_C0000,
190        MISCREG_MTRR_FIX_4K_C8000,
191        MISCREG_MTRR_FIX_4K_D0000,
192        MISCREG_MTRR_FIX_4K_D8000,
193        MISCREG_MTRR_FIX_4K_E0000,
194        MISCREG_MTRR_FIX_4K_E8000,
195        MISCREG_MTRR_FIX_4K_F0000,
196        MISCREG_MTRR_FIX_4K_F8000,
197
198        MISCREG_PAT,
199
200        MISCREG_DEF_TYPE,
201
202        MISCREG_MC_CTL_BASE,
203        MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
204        MISCREG_MC1_CTL,
205        MISCREG_MC2_CTL,
206        MISCREG_MC3_CTL,
207        MISCREG_MC4_CTL,
208        MISCREG_MC5_CTL,
209        MISCREG_MC6_CTL,
210        MISCREG_MC7_CTL,
211        MISCREG_MC_CTL_END,
212
213        MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END,
214        MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
215        MISCREG_MC1_STATUS,
216        MISCREG_MC2_STATUS,
217        MISCREG_MC3_STATUS,
218        MISCREG_MC4_STATUS,
219        MISCREG_MC5_STATUS,
220        MISCREG_MC6_STATUS,
221        MISCREG_MC7_STATUS,
222        MISCREG_MC_STATUS_END,
223
224        MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END,
225        MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
226        MISCREG_MC1_ADDR,
227        MISCREG_MC2_ADDR,
228        MISCREG_MC3_ADDR,
229        MISCREG_MC4_ADDR,
230        MISCREG_MC5_ADDR,
231        MISCREG_MC6_ADDR,
232        MISCREG_MC7_ADDR,
233        MISCREG_MC_ADDR_END,
234
235        MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END,
236        MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
237        MISCREG_MC1_MISC,
238        MISCREG_MC2_MISC,
239        MISCREG_MC3_MISC,
240        MISCREG_MC4_MISC,
241        MISCREG_MC5_MISC,
242        MISCREG_MC6_MISC,
243        MISCREG_MC7_MISC,
244        MISCREG_MC_MISC_END,
245
246        // Extended feature enable register
247        MISCREG_EFER = MISCREG_MC_MISC_END,
248
249        MISCREG_STAR,
250        MISCREG_LSTAR,
251        MISCREG_CSTAR,
252
253        MISCREG_SF_MASK,
254
255        MISCREG_KERNEL_GS_BASE,
256
257        MISCREG_TSC_AUX,
258
259        MISCREG_PERF_EVT_SEL_BASE,
260        MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
261        MISCREG_PERF_EVT_SEL1,
262        MISCREG_PERF_EVT_SEL2,
263        MISCREG_PERF_EVT_SEL3,
264        MISCREG_PERF_EVT_SEL_END,
265
266        MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END,
267        MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
268        MISCREG_PERF_EVT_CTR1,
269        MISCREG_PERF_EVT_CTR2,
270        MISCREG_PERF_EVT_CTR3,
271        MISCREG_PERF_EVT_CTR_END,
272
273        MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END,
274
275        MISCREG_IORR_BASE_BASE,
276        MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
277        MISCREG_IORR_BASE1,
278        MISCREG_IORR_BASE_END,
279
280        MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END,
281        MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
282        MISCREG_IORR_MASK1,
283        MISCREG_IORR_MASK_END,
284
285        MISCREG_TOP_MEM = MISCREG_IORR_MASK_END,
286        MISCREG_TOP_MEM2,
287
288        MISCREG_VM_CR,
289        MISCREG_IGNNE,
290        MISCREG_SMM_CTL,
291        MISCREG_VM_HSAVE_PA,
292
293        /*
294         * Segment registers
295         */
296        // Segment selectors
297        MISCREG_SEG_SEL_BASE,
298        MISCREG_ES = MISCREG_SEG_SEL_BASE,
299        MISCREG_CS,
300        MISCREG_SS,
301        MISCREG_DS,
302        MISCREG_FS,
303        MISCREG_GS,
304        MISCREG_HS,
305        MISCREG_TSL,
306        MISCREG_TSG,
307        MISCREG_LS,
308        MISCREG_MS,
309        MISCREG_TR,
310        MISCREG_IDTR,
311
312        // Hidden segment base field
313        MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
314        MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
315        MISCREG_CS_BASE,
316        MISCREG_SS_BASE,
317        MISCREG_DS_BASE,
318        MISCREG_FS_BASE,
319        MISCREG_GS_BASE,
320        MISCREG_HS_BASE,
321        MISCREG_TSL_BASE,
322        MISCREG_TSG_BASE,
323        MISCREG_LS_BASE,
324        MISCREG_MS_BASE,
325        MISCREG_TR_BASE,
326        MISCREG_IDTR_BASE,
327
328        // The effective segment base, ie what is actually added to an
329        // address. In 64 bit mode this can be different from the above,
330        // namely 0.
331        MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
332        MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
333        MISCREG_CS_EFF_BASE,
334        MISCREG_SS_EFF_BASE,
335        MISCREG_DS_EFF_BASE,
336        MISCREG_FS_EFF_BASE,
337        MISCREG_GS_EFF_BASE,
338        MISCREG_HS_EFF_BASE,
339        MISCREG_TSL_EFF_BASE,
340        MISCREG_TSG_EFF_BASE,
341        MISCREG_LS_EFF_BASE,
342        MISCREG_MS_EFF_BASE,
343        MISCREG_TR_EFF_BASE,
344        MISCREG_IDTR_EFF_BASE,
345
346        // Hidden segment limit field
347        MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
348        MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
349        MISCREG_CS_LIMIT,
350        MISCREG_SS_LIMIT,
351        MISCREG_DS_LIMIT,
352        MISCREG_FS_LIMIT,
353        MISCREG_GS_LIMIT,
354        MISCREG_HS_LIMIT,
355        MISCREG_TSL_LIMIT,
356        MISCREG_TSG_LIMIT,
357        MISCREG_LS_LIMIT,
358        MISCREG_MS_LIMIT,
359        MISCREG_TR_LIMIT,
360        MISCREG_IDTR_LIMIT,
361
362        // Hidden segment limit attributes
363        MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
364        MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
365        MISCREG_CS_ATTR,
366        MISCREG_SS_ATTR,
367        MISCREG_DS_ATTR,
368        MISCREG_FS_ATTR,
369        MISCREG_GS_ATTR,
370        MISCREG_HS_ATTR,
371        MISCREG_TSL_ATTR,
372        MISCREG_TSG_ATTR,
373        MISCREG_LS_ATTR,
374        MISCREG_MS_ATTR,
375        MISCREG_TR_ATTR,
376        MISCREG_IDTR_ATTR,
377
378        // Floating point control registers
379        MISCREG_X87_TOP =
380            MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
381
382        MISCREG_MXCSR,
383        MISCREG_FCW,
384        MISCREG_FSW,
385        MISCREG_FTW,
386        MISCREG_FTAG,
387        MISCREG_FISEG,
388        MISCREG_FIOFF,
389        MISCREG_FOSEG,
390        MISCREG_FOOFF,
391        MISCREG_FOP,
392
393        //XXX Add "Model-Specific Registers"
394
395        MISCREG_APIC_BASE,
396
397        // "Fake" MSRs for internally implemented devices
398        MISCREG_PCI_CONFIG_ADDRESS,
399
400        NUM_MISCREGS
401    };
402
403    static inline bool
404    isValidMiscReg(int index)
405    {
406        return (index >= MISCREG_CR0 && index < NUM_MISCREGS &&
407                index != MISCREG_CR1 &&
408                !(index > MISCREG_CR4 && index < MISCREG_CR8) &&
409                !(index > MISCREG_CR8 && index <= MISCREG_CR15));
410    }
411
412    static inline MiscRegIndex
413    MISCREG_CR(int index)
414    {
415        assert(index >= 0 && index < NumCRegs);
416        return (MiscRegIndex)(MISCREG_CR_BASE + index);
417    }
418
419    static inline MiscRegIndex
420    MISCREG_DR(int index)
421    {
422        assert(index >= 0 && index < NumDRegs);
423        return (MiscRegIndex)(MISCREG_DR_BASE + index);
424    }
425
426    static inline MiscRegIndex
427    MISCREG_MTRR_PHYS_BASE(int index)
428    {
429        assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END -
430                                      MISCREG_MTRR_PHYS_BASE_BASE));
431        return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
432    }
433
434    static inline MiscRegIndex
435    MISCREG_MTRR_PHYS_MASK(int index)
436    {
437        assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END -
438                                      MISCREG_MTRR_PHYS_MASK_BASE));
439        return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
440    }
441
442    static inline MiscRegIndex
443    MISCREG_MC_CTL(int index)
444    {
445        assert(index >= 0 && index < (MISCREG_MC_CTL_END -
446                                      MISCREG_MC_CTL_BASE));
447        return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
448    }
449
450    static inline MiscRegIndex
451    MISCREG_MC_STATUS(int index)
452    {
453        assert(index >= 0 && index < (MISCREG_MC_STATUS_END -
454                                      MISCREG_MC_STATUS_BASE));
455        return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
456    }
457
458    static inline MiscRegIndex
459    MISCREG_MC_ADDR(int index)
460    {
461        assert(index >= 0 && index < (MISCREG_MC_ADDR_END -
462                                      MISCREG_MC_ADDR_BASE));
463        return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
464    }
465
466    static inline MiscRegIndex
467    MISCREG_MC_MISC(int index)
468    {
469        assert(index >= 0 && index < (MISCREG_MC_MISC_END -
470                                      MISCREG_MC_MISC_BASE));
471        return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
472    }
473
474    static inline MiscRegIndex
475    MISCREG_PERF_EVT_SEL(int index)
476    {
477        assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END -
478                                      MISCREG_PERF_EVT_SEL_BASE));
479        return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
480    }
481
482    static inline MiscRegIndex
483    MISCREG_PERF_EVT_CTR(int index)
484    {
485        assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END -
486                                      MISCREG_PERF_EVT_CTR_BASE));
487        return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
488    }
489
490    static inline MiscRegIndex
491    MISCREG_IORR_BASE(int index)
492    {
493        assert(index >= 0 && index < (MISCREG_IORR_BASE_END -
494                                      MISCREG_IORR_BASE_BASE));
495        return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
496    }
497
498    static inline MiscRegIndex
499    MISCREG_IORR_MASK(int index)
500    {
501        assert(index >= 0 && index < (MISCREG_IORR_MASK_END -
502                                      MISCREG_IORR_MASK_BASE));
503        return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
504    }
505
506    static inline MiscRegIndex
507    MISCREG_SEG_SEL(int index)
508    {
509        assert(index >= 0 && index < NUM_SEGMENTREGS);
510        return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
511    }
512
513    static inline MiscRegIndex
514    MISCREG_SEG_BASE(int index)
515    {
516        assert(index >= 0 && index < NUM_SEGMENTREGS);
517        return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
518    }
519
520    static inline MiscRegIndex
521    MISCREG_SEG_EFF_BASE(int index)
522    {
523        assert(index >= 0 && index < NUM_SEGMENTREGS);
524        return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
525    }
526
527    static inline MiscRegIndex
528    MISCREG_SEG_LIMIT(int index)
529    {
530        assert(index >= 0 && index < NUM_SEGMENTREGS);
531        return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
532    }
533
534    static inline MiscRegIndex
535    MISCREG_SEG_ATTR(int index)
536    {
537        assert(index >= 0 && index < NUM_SEGMENTREGS);
538        return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
539    }
540
541    /**
542     * A type to describe the condition code bits of the RFLAGS register,
543     * plus two flags, EZF and ECF, which are only visible to microcode.
544     */
545    BitUnion64(CCFlagBits)
546        Bitfield<11> of;
547        Bitfield<7> sf;
548        Bitfield<6> zf;
549        Bitfield<5> ezf;
550        Bitfield<4> af;
551        Bitfield<3> ecf;
552        Bitfield<2> pf;
553        Bitfield<0> cf;
554    EndBitUnion(CCFlagBits)
555
556    /**
557     * RFLAGS
558     */
559    BitUnion64(RFLAGS)
560        Bitfield<21> id; // ID Flag
561        Bitfield<20> vip; // Virtual Interrupt Pending
562        Bitfield<19> vif; // Virtual Interrupt Flag
563        Bitfield<18> ac; // Alignment Check
564        Bitfield<17> vm; // Virtual-8086 Mode
565        Bitfield<16> rf; // Resume Flag
566        Bitfield<14> nt; // Nested Task
567        Bitfield<13, 12> iopl; // I/O Privilege Level
568        Bitfield<11> of; // Overflow Flag
569        Bitfield<10> df; // Direction Flag
570        Bitfield<9> intf; // Interrupt Flag
571        Bitfield<8> tf; // Trap Flag
572        Bitfield<7> sf; // Sign Flag
573        Bitfield<6> zf; // Zero Flag
574        Bitfield<4> af; // Auxiliary Flag
575        Bitfield<2> pf; // Parity Flag
576        Bitfield<0> cf; // Carry Flag
577    EndBitUnion(RFLAGS)
578
579    BitUnion64(HandyM5Reg)
580        Bitfield<0> mode;
581        Bitfield<3, 1> submode;
582        Bitfield<5, 4> cpl;
583        Bitfield<6> paging;
584        Bitfield<7> prot;
585        Bitfield<9, 8> defOp;
586        Bitfield<11, 10> altOp;
587        Bitfield<13, 12> defAddr;
588        Bitfield<15, 14> altAddr;
589        Bitfield<17, 16> stack;
590    EndBitUnion(HandyM5Reg)
591
592    /**
593     * Control registers
594     */
595    BitUnion64(CR0)
596        Bitfield<31> pg; // Paging
597        Bitfield<30> cd; // Cache Disable
598        Bitfield<29> nw; // Not Writethrough
599        Bitfield<18> am; // Alignment Mask
600        Bitfield<16> wp; // Write Protect
601        Bitfield<5> ne; // Numeric Error
602        Bitfield<4> et; // Extension Type
603        Bitfield<3> ts; // Task Switched
604        Bitfield<2> em; // Emulation
605        Bitfield<1> mp; // Monitor Coprocessor
606        Bitfield<0> pe; // Protection Enabled
607    EndBitUnion(CR0)
608
609    // Page Fault Virtual Address
610    BitUnion64(CR2)
611        Bitfield<31, 0> legacy;
612    EndBitUnion(CR2)
613
614    BitUnion64(CR3)
615        Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
616                                   // Base Address
617        Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
618                               // Base Address
619        Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
620                                 // Base Address
621        Bitfield<4> pcd; // Page-Level Cache Disable
622        Bitfield<3> pwt; // Page-Level Writethrough
623    EndBitUnion(CR3)
624
625    BitUnion64(CR4)
626        Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States
627        Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE,
628                               // WRGSBASE instructions
629        Bitfield<10> osxmmexcpt; // Operating System Unmasked
630                                 // Exception Support
631        Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
632        Bitfield<8> pce; // Performance-Monitoring Counter Enable
633        Bitfield<7> pge; // Page-Global Enable
634        Bitfield<6> mce; // Machine Check Enable
635        Bitfield<5> pae; // Physical-Address Extension
636        Bitfield<4> pse; // Page Size Extensions
637        Bitfield<3> de; // Debugging Extensions
638        Bitfield<2> tsd; // Time Stamp Disable
639        Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
640        Bitfield<0> vme; // Virtual-8086 Mode Extensions
641    EndBitUnion(CR4)
642
643    BitUnion64(CR8)
644        Bitfield<3, 0> tpr; // Task Priority Register
645    EndBitUnion(CR8)
646
647    BitUnion64(DR6)
648        Bitfield<0> b0;
649        Bitfield<1> b1;
650        Bitfield<2> b2;
651        Bitfield<3> b3;
652        Bitfield<13> bd;
653        Bitfield<14> bs;
654        Bitfield<15> bt;
655    EndBitUnion(DR6)
656
657    BitUnion64(DR7)
658        Bitfield<0> l0;
659        Bitfield<1> g0;
660        Bitfield<2> l1;
661        Bitfield<3> g1;
662        Bitfield<4> l2;
663        Bitfield<5> g2;
664        Bitfield<6> l3;
665        Bitfield<7> g3;
666        Bitfield<8> le;
667        Bitfield<9> ge;
668        Bitfield<13> gd;
669        Bitfield<17, 16> rw0;
670        Bitfield<19, 18> len0;
671        Bitfield<21, 20> rw1;
672        Bitfield<23, 22> len1;
673        Bitfield<25, 24> rw2;
674        Bitfield<27, 26> len2;
675        Bitfield<29, 28> rw3;
676        Bitfield<31, 30> len3;
677    EndBitUnion(DR7)
678
679    // MTRR capabilities
680    BitUnion64(MTRRcap)
681        Bitfield<7, 0> vcnt; // Variable-Range Register Count
682        Bitfield<8> fix; // Fixed-Range Registers
683        Bitfield<10> wc; // Write-Combining
684    EndBitUnion(MTRRcap)
685
686    /**
687     * SYSENTER configuration registers
688     */
689    BitUnion64(SysenterCS)
690        Bitfield<15, 0> targetCS;
691    EndBitUnion(SysenterCS)
692
693    BitUnion64(SysenterESP)
694        Bitfield<31, 0> targetESP;
695    EndBitUnion(SysenterESP)
696
697    BitUnion64(SysenterEIP)
698        Bitfield<31, 0> targetEIP;
699    EndBitUnion(SysenterEIP)
700
701    /**
702     * Global machine check registers
703     */
704    BitUnion64(McgCap)
705        Bitfield<7, 0> count; // Number of error reporting register banks
706        Bitfield<8> MCGCP; // MCG_CTL register present.
707    EndBitUnion(McgCap)
708
709    BitUnion64(McgStatus)
710        Bitfield<0> ripv; // Restart-IP valid
711        Bitfield<1> eipv; // Error-IP valid
712        Bitfield<2> mcip; // Machine check in-progress
713    EndBitUnion(McgStatus)
714
715    BitUnion64(DebugCtlMsr)
716        Bitfield<0> lbr; // Last-branch record
717        Bitfield<1> btf; // Branch single step
718        Bitfield<2> pb0; // Performance monitoring pin control 0
719        Bitfield<3> pb1; // Performance monitoring pin control 1
720        Bitfield<4> pb2; // Performance monitoring pin control 2
721        Bitfield<5> pb3; // Performance monitoring pin control 3
722        /*uint64_t pb(int index)
723        {
724            return bits(__data, index + 2);
725        }*/
726    EndBitUnion(DebugCtlMsr)
727
728    BitUnion64(MtrrPhysBase)
729        Bitfield<7, 0> type; // Default memory type
730        Bitfield<51, 12> physbase; // Range physical base address
731    EndBitUnion(MtrrPhysBase)
732
733    BitUnion64(MtrrPhysMask)
734        Bitfield<11> valid; // MTRR pair enable
735        Bitfield<51, 12> physmask; // Range physical mask
736    EndBitUnion(MtrrPhysMask)
737
738    BitUnion64(MtrrFixed)
739        /*uint64_t type(int index)
740        {
741            return bits(__data, index * 8 + 7, index * 8);
742        }*/
743    EndBitUnion(MtrrFixed)
744
745    BitUnion64(Pat)
746        /*uint64_t pa(int index)
747        {
748            return bits(__data, index * 8 + 2, index * 8);
749        }*/
750    EndBitUnion(Pat)
751
752    BitUnion64(MtrrDefType)
753        Bitfield<7, 0> type; // Default type
754        Bitfield<10> fe; // Fixed range enable
755        Bitfield<11> e; // MTRR enable
756    EndBitUnion(MtrrDefType)
757
758    /**
759     * Machine check
760     */
761    BitUnion64(McStatus)
762        Bitfield<15,0> mcaErrorCode;
763        Bitfield<31,16> modelSpecificCode;
764        Bitfield<56,32> otherInfo;
765        Bitfield<57> pcc; // Processor-context corrupt
766        Bitfield<58> addrv; // Error-address register valid
767        Bitfield<59> miscv; // Miscellaneous-error register valid
768        Bitfield<60> en; // Error condition enabled
769        Bitfield<61> uc; // Uncorrected error
770        Bitfield<62> over; // Status register overflow
771        Bitfield<63> val; // Valid
772    EndBitUnion(McStatus)
773
774    BitUnion64(McCtl)
775        /*uint64_t en(int index)
776        {
777            return bits(__data, index);
778        }*/
779    EndBitUnion(McCtl)
780
781    // Extended feature enable register
782    BitUnion64(Efer)
783        Bitfield<0> sce; // System call extensions
784        Bitfield<8> lme; // Long mode enable
785        Bitfield<10> lma; // Long mode active
786        Bitfield<11> nxe; // No-execute enable
787        Bitfield<12> svme; // Secure virtual machine enable
788        Bitfield<14> ffxsr; // Fast fxsave/fxrstor
789    EndBitUnion(Efer)
790
791    BitUnion64(Star)
792        Bitfield<31,0> targetEip;
793        Bitfield<47,32> syscallCsAndSs;
794        Bitfield<63,48> sysretCsAndSs;
795    EndBitUnion(Star)
796
797    BitUnion64(SfMask)
798        Bitfield<31,0> mask;
799    EndBitUnion(SfMask)
800
801    BitUnion64(PerfEvtSel)
802        Bitfield<7,0> eventMask;
803        Bitfield<15,8> unitMask;
804        Bitfield<16> usr; // User mode
805        Bitfield<17> os; // Operating-system mode
806        Bitfield<18> e; // Edge detect
807        Bitfield<19> pc; // Pin control
808        Bitfield<20> intEn; // Interrupt enable
809        Bitfield<22> en; // Counter enable
810        Bitfield<23> inv; // Invert mask
811        Bitfield<31,24> counterMask;
812    EndBitUnion(PerfEvtSel)
813
814    BitUnion32(Syscfg)
815        Bitfield<18> mfde; // MtrrFixDramEn
816        Bitfield<19> mfdm; // MtrrFixDramModEn
817        Bitfield<20> mvdm; // MtrrVarDramEn
818        Bitfield<21> tom2; // MtrrTom2En
819    EndBitUnion(Syscfg)
820
821    BitUnion64(IorrBase)
822        Bitfield<3> wr; // WrMem Enable
823        Bitfield<4> rd; // RdMem Enable
824        Bitfield<51,12> physbase; // Range physical base address
825    EndBitUnion(IorrBase)
826
827    BitUnion64(IorrMask)
828        Bitfield<11> v; // I/O register pair enable (valid)
829        Bitfield<51,12> physmask; // Range physical mask
830    EndBitUnion(IorrMask)
831
832    BitUnion64(Tom)
833        Bitfield<51,23> physAddr; // Top of memory physical address
834    EndBitUnion(Tom)
835
836    BitUnion64(VmCrMsr)
837        Bitfield<0> dpd;
838        Bitfield<1> rInit;
839        Bitfield<2> disA20M;
840    EndBitUnion(VmCrMsr)
841
842    BitUnion64(IgnneMsr)
843        Bitfield<0> ignne;
844    EndBitUnion(IgnneMsr)
845
846    BitUnion64(SmmCtlMsr)
847        Bitfield<0> dismiss;
848        Bitfield<1> enter;
849        Bitfield<2> smiCycle;
850        Bitfield<3> exit;
851        Bitfield<4> rsmCycle;
852    EndBitUnion(SmmCtlMsr)
853
854    /**
855     * Segment Selector
856     */
857    BitUnion64(SegSelector)
858        // The following bitfield is not defined in the ISA, but it's useful
859        // when checking selectors in larger data types to make sure they
860        // aren't too large.
861        Bitfield<63, 3> esi; // Extended selector
862        Bitfield<15, 3> si; // Selector Index
863        Bitfield<2> ti; // Table Indicator
864        Bitfield<1, 0> rpl; // Requestor Privilege Level
865    EndBitUnion(SegSelector)
866
867    /**
868     * Segment Descriptors
869     */
870
871    class SegDescriptorBase
872    {
873      public:
874        uint32_t
875        getter(const uint64_t &storage) const
876        {
877            return (bits(storage, 63, 56) << 24) | bits(storage, 39, 16);
878        }
879
880        void
881        setter(uint64_t &storage, uint32_t base)
882        {
883            replaceBits(storage, 63, 56, bits(base, 31, 24));
884            replaceBits(storage, 39, 16, bits(base, 23, 0));
885        }
886    };
887
888    class SegDescriptorLimit
889    {
890      public:
891        uint32_t
892        getter(const uint64_t &storage) const
893        {
894            uint32_t limit = (bits(storage, 51, 48) << 16) |
895                             bits(storage, 15, 0);
896            if (bits(storage, 55))
897                limit = (limit << 12) | mask(12);
898            return limit;
899        }
900
901        void
902        setter(uint64_t &storage, uint32_t limit)
903        {
904            bool g = (bits(limit, 31, 24) != 0);
905            panic_if(g && bits(limit, 11, 0) != mask(12),
906                     "Inlimitid segment limit %#x", limit);
907            if (g)
908                limit = limit >> 12;
909            replaceBits(storage, 51, 48, bits(limit, 23, 16));
910            replaceBits(storage, 15, 0, bits(limit, 15, 0));
911            replaceBits(storage, 55, g ? 1 : 0);
912        }
913    };
914
915    BitUnion64(SegDescriptor)
916        Bitfield<63, 56> baseHigh;
917        Bitfield<39, 16> baseLow;
918        BitfieldType<SegDescriptorBase> base;
919        Bitfield<55> g; // Granularity
920        Bitfield<54> d; // Default Operand Size
921        Bitfield<54> b; // Default Operand Size
922        Bitfield<53> l; // Long Attribute Bit
923        Bitfield<52> avl; // Available To Software
924        Bitfield<51, 48> limitHigh;
925        Bitfield<15, 0> limitLow;
926        BitfieldType<SegDescriptorLimit> limit;
927        Bitfield<47> p; // Present
928        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
929        Bitfield<44> s; // System
930        SubBitUnion(type, 43, 40)
931            // Specifies whether this descriptor is for code or data.
932            Bitfield<43> codeOrData;
933
934            // These bit fields are for code segments
935            Bitfield<42> c; // Conforming
936            Bitfield<41> r; // Readable
937
938            // These bit fields are for data segments
939            Bitfield<42> e; // Expand-Down
940            Bitfield<41> w; // Writable
941
942            // This is used for both code and data segments.
943            Bitfield<40> a; // Accessed
944        EndSubBitUnion(type)
945    EndBitUnion(SegDescriptor)
946
947    /**
948     * TSS Descriptor (long mode - 128 bits)
949     * the lower 64 bits
950     */
951    BitUnion64(TSSlow)
952        Bitfield<63, 56> baseHigh;
953        Bitfield<39, 16> baseLow;
954        BitfieldType<SegDescriptorBase> base;
955        Bitfield<55> g; // Granularity
956        Bitfield<52> avl; // Available To Software
957        Bitfield<51, 48> limitHigh;
958        Bitfield<15, 0> limitLow;
959        BitfieldType<SegDescriptorLimit> limit;
960        Bitfield<47> p; // Present
961        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
962        SubBitUnion(type, 43, 40)
963            // Specifies whether this descriptor is for code or data.
964            Bitfield<43> codeOrData;
965
966            // These bit fields are for code segments
967            Bitfield<42> c; // Conforming
968            Bitfield<41> r; // Readable
969
970            // These bit fields are for data segments
971            Bitfield<42> e; // Expand-Down
972            Bitfield<41> w; // Writable
973
974            // This is used for both code and data segments.
975            Bitfield<40> a; // Accessed
976        EndSubBitUnion(type)
977    EndBitUnion(TSSlow)
978
979    /**
980     * TSS Descriptor (long mode - 128 bits)
981     * the upper 64 bits
982     */
983    BitUnion64(TSShigh)
984        Bitfield<31, 0> base;
985    EndBitUnion(TSShigh)
986
987    BitUnion64(SegAttr)
988        Bitfield<1, 0> dpl;
989        Bitfield<2> unusable;
990        Bitfield<3> defaultSize;
991        Bitfield<4> longMode;
992        Bitfield<5> avl;
993        Bitfield<6> granularity;
994        Bitfield<7> present;
995        Bitfield<11, 8> type;
996        Bitfield<12> writable;
997        Bitfield<13> readable;
998        Bitfield<14> expandDown;
999        Bitfield<15> system;
1000    EndBitUnion(SegAttr)
1001
1002    BitUnion64(GateDescriptor)
1003        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1004        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1005        Bitfield<31, 16> selector; // Target Code-Segment Selector
1006        Bitfield<47> p; // Present
1007        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1008        Bitfield<43, 40> type;
1009        Bitfield<36, 32> count; // Parameter Count
1010    EndBitUnion(GateDescriptor)
1011
1012    /**
1013     * Long Mode Gate Descriptor
1014     */
1015    BitUnion64(GateDescriptorLow)
1016        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
1017        Bitfield<47> p; // Present
1018        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
1019        Bitfield<43, 40> type;
1020        Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling
1021        Bitfield<31, 16> selector; // Target Code-Segment Selector
1022        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
1023    EndBitUnion(GateDescriptorLow)
1024
1025    BitUnion64(GateDescriptorHigh)
1026        Bitfield<31, 0> offset; // Target Code-Segment Offset
1027    EndBitUnion(GateDescriptorHigh)
1028
1029    /**
1030     * Descriptor-Table Registers
1031     */
1032    BitUnion64(GDTR)
1033    EndBitUnion(GDTR)
1034
1035    BitUnion64(IDTR)
1036    EndBitUnion(IDTR)
1037
1038    BitUnion64(LDTR)
1039    EndBitUnion(LDTR)
1040
1041    /**
1042     * Task Register
1043     */
1044    BitUnion64(TR)
1045    EndBitUnion(TR)
1046
1047
1048    /**
1049     * Local APIC Base Register
1050     */
1051    BitUnion64(LocalApicBase)
1052        Bitfield<51, 12> base;
1053        Bitfield<11> enable;
1054        Bitfield<8> bsp;
1055    EndBitUnion(LocalApicBase)
1056}
1057
1058#endif // __ARCH_X86_INTREGS_HH__
1059