14684SN/A/* 25419SN/A * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 34684SN/A * All rights reserved. 44684SN/A * 57087SN/A * The license below extends only to copyright in the software and shall 67087SN/A * not be construed as granting a license to any other intellectual 77087SN/A * property including but not limited to intellectual property relating 87087SN/A * to a hardware implementation of the functionality of the software 97087SN/A * licensed hereunder. You may use the software subject to the license 107087SN/A * terms below provided that you ensure that this notice is replicated 117087SN/A * unmodified and in its entirety in all distributions of the software, 127087SN/A * modified or unmodified, in source code or in binary form. 134684SN/A * 147087SN/A * Redistribution and use in source and binary forms, with or without 157087SN/A * modification, are permitted provided that the following conditions are 167087SN/A * met: redistributions of source code must retain the above copyright 177087SN/A * notice, this list of conditions and the following disclaimer; 187087SN/A * redistributions in binary form must reproduce the above copyright 197087SN/A * notice, this list of conditions and the following disclaimer in the 207087SN/A * documentation and/or other materials provided with the distribution; 217087SN/A * neither the name of the copyright holders nor the names of its 224684SN/A * contributors may be used to endorse or promote products derived from 237087SN/A * this software without specific prior written permission. 244684SN/A * 254684SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 264684SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 274684SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 284684SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 294684SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 304684SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 314684SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 324684SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 334684SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 344684SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 354684SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 364684SN/A * 374684SN/A * Authors: Gabe Black 384684SN/A */ 394684SN/A 404684SN/A#ifndef __ARCH_X86_MISCREGS_HH__ 414684SN/A#define __ARCH_X86_MISCREGS_HH__ 424684SN/A 437629Sgblack@eecs.umich.edu#include "arch/x86/regs/segment.hh" 445025SN/A#include "arch/x86/x86_traits.hh" 454684SN/A#include "base/bitunion.hh" 4612588Sgabeblack@google.com#include "base/logging.hh" 474684SN/A 485086SN/A//These get defined in some system headers (at least termbits.h). That confuses 495086SN/A//things here significantly. 505086SN/A#undef CR0 515086SN/A#undef CR2 525086SN/A#undef CR3 535086SN/A 544684SN/Anamespace X86ISA 554684SN/A{ 564684SN/A enum CondFlagBit { 574684SN/A CFBit = 1 << 0, 584684SN/A PFBit = 1 << 2, 594684SN/A ECFBit = 1 << 3, 604684SN/A AFBit = 1 << 4, 614684SN/A EZFBit = 1 << 5, 624684SN/A ZFBit = 1 << 6, 634684SN/A SFBit = 1 << 7, 644868SN/A DFBit = 1 << 10, 654684SN/A OFBit = 1 << 11 664684SN/A }; 674684SN/A 689010Snilay@cs.wisc.edu const uint32_t cfofMask = CFBit | OFBit; 699211Snilay@cs.wisc.edu const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit; 709010Snilay@cs.wisc.edu 715426SN/A enum RFLAGBit { 725426SN/A TFBit = 1 << 8, 735426SN/A IFBit = 1 << 9, 745426SN/A NTBit = 1 << 14, 755426SN/A RFBit = 1 << 16, 765426SN/A VMBit = 1 << 17, 775426SN/A ACBit = 1 << 18, 785426SN/A VIFBit = 1 << 19, 795426SN/A VIPBit = 1 << 20, 805426SN/A IDBit = 1 << 21 815426SN/A }; 825426SN/A 839470Snilay@cs.wisc.edu enum X87StatusBit { 849470Snilay@cs.wisc.edu // Exception Flags 859470Snilay@cs.wisc.edu IEBit = 1 << 0, 869470Snilay@cs.wisc.edu DEBit = 1 << 1, 879470Snilay@cs.wisc.edu ZEBit = 1 << 2, 889470Snilay@cs.wisc.edu OEBit = 1 << 3, 899470Snilay@cs.wisc.edu UEBit = 1 << 4, 909470Snilay@cs.wisc.edu PEBit = 1 << 5, 919470Snilay@cs.wisc.edu 929470Snilay@cs.wisc.edu // !Exception Flags 939470Snilay@cs.wisc.edu StackFaultBit = 1 << 6, 949470Snilay@cs.wisc.edu ErrSummaryBit = 1 << 7, 959470Snilay@cs.wisc.edu CC0Bit = 1 << 8, 969470Snilay@cs.wisc.edu CC1Bit = 1 << 9, 979470Snilay@cs.wisc.edu CC2Bit = 1 << 10, 989470Snilay@cs.wisc.edu CC3Bit = 1 << 14, 999470Snilay@cs.wisc.edu BusyBit = 1 << 15, 1009470Snilay@cs.wisc.edu }; 1019470Snilay@cs.wisc.edu 1024700SN/A enum MiscRegIndex 1034700SN/A { 1044700SN/A // Control registers 10511324Ssteve.reinhardt@amd.com // Most of these are invalid. See isValidMiscReg() below. 1064862SN/A MISCREG_CR_BASE, 1074862SN/A MISCREG_CR0 = MISCREG_CR_BASE, 1084700SN/A MISCREG_CR1, 1094700SN/A MISCREG_CR2, 1104700SN/A MISCREG_CR3, 1114700SN/A MISCREG_CR4, 1124700SN/A MISCREG_CR5, 1134700SN/A MISCREG_CR6, 1144700SN/A MISCREG_CR7, 1154700SN/A MISCREG_CR8, 1164700SN/A MISCREG_CR9, 1174700SN/A MISCREG_CR10, 1184700SN/A MISCREG_CR11, 1194700SN/A MISCREG_CR12, 1204700SN/A MISCREG_CR13, 1214700SN/A MISCREG_CR14, 1224700SN/A MISCREG_CR15, 1234700SN/A 1244700SN/A // Debug registers 1255025SN/A MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 1264862SN/A MISCREG_DR0 = MISCREG_DR_BASE, 1274700SN/A MISCREG_DR1, 1284700SN/A MISCREG_DR2, 1294700SN/A MISCREG_DR3, 1304700SN/A MISCREG_DR4, 1314700SN/A MISCREG_DR5, 1324700SN/A MISCREG_DR6, 1334700SN/A MISCREG_DR7, 1344700SN/A 1354700SN/A // Flags register 1365025SN/A MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 1374700SN/A 1385429SN/A //Register to keep handy values like the CPU mode in. 1395429SN/A MISCREG_M5_REG, 1405429SN/A 1415138SN/A /* 1425138SN/A * Model Specific Registers 1435138SN/A */ 1445138SN/A // Time stamp counter 1455138SN/A MISCREG_TSC, 1465138SN/A 1475138SN/A MISCREG_MTRRCAP, 1485138SN/A 1495138SN/A MISCREG_SYSENTER_CS, 1505138SN/A MISCREG_SYSENTER_ESP, 1515138SN/A MISCREG_SYSENTER_EIP, 1525138SN/A 1535138SN/A MISCREG_MCG_CAP, 1545138SN/A MISCREG_MCG_STATUS, 1555138SN/A MISCREG_MCG_CTL, 1565138SN/A 1575138SN/A MISCREG_DEBUG_CTL_MSR, 1585138SN/A 1595138SN/A MISCREG_LAST_BRANCH_FROM_IP, 1605138SN/A MISCREG_LAST_BRANCH_TO_IP, 1615138SN/A MISCREG_LAST_EXCEPTION_FROM_IP, 1625138SN/A MISCREG_LAST_EXCEPTION_TO_IP, 1635138SN/A 1645138SN/A MISCREG_MTRR_PHYS_BASE_BASE, 1655138SN/A MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 1665138SN/A MISCREG_MTRR_PHYS_BASE_1, 1675138SN/A MISCREG_MTRR_PHYS_BASE_2, 1685138SN/A MISCREG_MTRR_PHYS_BASE_3, 1695138SN/A MISCREG_MTRR_PHYS_BASE_4, 1705138SN/A MISCREG_MTRR_PHYS_BASE_5, 1715138SN/A MISCREG_MTRR_PHYS_BASE_6, 1725138SN/A MISCREG_MTRR_PHYS_BASE_7, 1736346SN/A MISCREG_MTRR_PHYS_BASE_END, 1745138SN/A 1756346SN/A MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, 1765138SN/A MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 1775138SN/A MISCREG_MTRR_PHYS_MASK_1, 1785138SN/A MISCREG_MTRR_PHYS_MASK_2, 1795138SN/A MISCREG_MTRR_PHYS_MASK_3, 1805138SN/A MISCREG_MTRR_PHYS_MASK_4, 1815138SN/A MISCREG_MTRR_PHYS_MASK_5, 1825138SN/A MISCREG_MTRR_PHYS_MASK_6, 1835138SN/A MISCREG_MTRR_PHYS_MASK_7, 1846346SN/A MISCREG_MTRR_PHYS_MASK_END, 1855138SN/A 1866346SN/A MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, 1875138SN/A MISCREG_MTRR_FIX_16K_80000, 1885138SN/A MISCREG_MTRR_FIX_16K_A0000, 1895138SN/A MISCREG_MTRR_FIX_4K_C0000, 1905149SN/A MISCREG_MTRR_FIX_4K_C8000, 1915138SN/A MISCREG_MTRR_FIX_4K_D0000, 1925138SN/A MISCREG_MTRR_FIX_4K_D8000, 1935138SN/A MISCREG_MTRR_FIX_4K_E0000, 1945138SN/A MISCREG_MTRR_FIX_4K_E8000, 1955138SN/A MISCREG_MTRR_FIX_4K_F0000, 1965138SN/A MISCREG_MTRR_FIX_4K_F8000, 1975138SN/A 1985138SN/A MISCREG_PAT, 1995138SN/A 2005138SN/A MISCREG_DEF_TYPE, 2015138SN/A 2025138SN/A MISCREG_MC_CTL_BASE, 2035138SN/A MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 2045138SN/A MISCREG_MC1_CTL, 2055138SN/A MISCREG_MC2_CTL, 2065138SN/A MISCREG_MC3_CTL, 2075138SN/A MISCREG_MC4_CTL, 2085419SN/A MISCREG_MC5_CTL, 2095419SN/A MISCREG_MC6_CTL, 2105419SN/A MISCREG_MC7_CTL, 2116346SN/A MISCREG_MC_CTL_END, 2125138SN/A 2136346SN/A MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, 2145138SN/A MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 2155138SN/A MISCREG_MC1_STATUS, 2165138SN/A MISCREG_MC2_STATUS, 2175138SN/A MISCREG_MC3_STATUS, 2185138SN/A MISCREG_MC4_STATUS, 2195419SN/A MISCREG_MC5_STATUS, 2205419SN/A MISCREG_MC6_STATUS, 2215419SN/A MISCREG_MC7_STATUS, 2226346SN/A MISCREG_MC_STATUS_END, 2235138SN/A 2246346SN/A MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, 2255138SN/A MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 2265138SN/A MISCREG_MC1_ADDR, 2275138SN/A MISCREG_MC2_ADDR, 2285138SN/A MISCREG_MC3_ADDR, 2295138SN/A MISCREG_MC4_ADDR, 2305419SN/A MISCREG_MC5_ADDR, 2315419SN/A MISCREG_MC6_ADDR, 2325419SN/A MISCREG_MC7_ADDR, 2336346SN/A MISCREG_MC_ADDR_END, 2345138SN/A 2356346SN/A MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, 2365138SN/A MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 2375138SN/A MISCREG_MC1_MISC, 2385138SN/A MISCREG_MC2_MISC, 2395138SN/A MISCREG_MC3_MISC, 2405138SN/A MISCREG_MC4_MISC, 2415419SN/A MISCREG_MC5_MISC, 2425419SN/A MISCREG_MC6_MISC, 2435419SN/A MISCREG_MC7_MISC, 2446346SN/A MISCREG_MC_MISC_END, 2455138SN/A 2465135SN/A // Extended feature enable register 2476346SN/A MISCREG_EFER = MISCREG_MC_MISC_END, 2485135SN/A 2495138SN/A MISCREG_STAR, 2505138SN/A MISCREG_LSTAR, 2515138SN/A MISCREG_CSTAR, 2525138SN/A 2535138SN/A MISCREG_SF_MASK, 2545138SN/A 2555138SN/A MISCREG_KERNEL_GS_BASE, 2565138SN/A 2575138SN/A MISCREG_TSC_AUX, 2585138SN/A 2595138SN/A MISCREG_PERF_EVT_SEL_BASE, 2605138SN/A MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 2615138SN/A MISCREG_PERF_EVT_SEL1, 2625138SN/A MISCREG_PERF_EVT_SEL2, 2635138SN/A MISCREG_PERF_EVT_SEL3, 2646346SN/A MISCREG_PERF_EVT_SEL_END, 2655138SN/A 2666346SN/A MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, 2675138SN/A MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 2685138SN/A MISCREG_PERF_EVT_CTR1, 2695138SN/A MISCREG_PERF_EVT_CTR2, 2705138SN/A MISCREG_PERF_EVT_CTR3, 2716346SN/A MISCREG_PERF_EVT_CTR_END, 2725138SN/A 2736346SN/A MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, 2745138SN/A 2755138SN/A MISCREG_IORR_BASE_BASE, 2765138SN/A MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 2775138SN/A MISCREG_IORR_BASE1, 2786346SN/A MISCREG_IORR_BASE_END, 2795138SN/A 2806346SN/A MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, 2815138SN/A MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 2825138SN/A MISCREG_IORR_MASK1, 2836346SN/A MISCREG_IORR_MASK_END, 2845138SN/A 2856346SN/A MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, 2865138SN/A MISCREG_TOP_MEM2, 2875138SN/A 2885138SN/A MISCREG_VM_CR, 2895138SN/A MISCREG_IGNNE, 2905138SN/A MISCREG_SMM_CTL, 2915138SN/A MISCREG_VM_HSAVE_PA, 2925138SN/A 2935138SN/A /* 2945138SN/A * Segment registers 2955138SN/A */ 2964700SN/A // Segment selectors 2974862SN/A MISCREG_SEG_SEL_BASE, 2984862SN/A MISCREG_ES = MISCREG_SEG_SEL_BASE, 2994700SN/A MISCREG_CS, 3004700SN/A MISCREG_SS, 3014700SN/A MISCREG_DS, 3024700SN/A MISCREG_FS, 3034700SN/A MISCREG_GS, 3045294SN/A MISCREG_HS, 3055294SN/A MISCREG_TSL, 3065294SN/A MISCREG_TSG, 3075294SN/A MISCREG_LS, 3085294SN/A MISCREG_MS, 3095294SN/A MISCREG_TR, 3105294SN/A MISCREG_IDTR, 3114700SN/A 3124700SN/A // Hidden segment base field 3135294SN/A MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 3144862SN/A MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 3154700SN/A MISCREG_CS_BASE, 3164700SN/A MISCREG_SS_BASE, 3174700SN/A MISCREG_DS_BASE, 3184700SN/A MISCREG_FS_BASE, 3194700SN/A MISCREG_GS_BASE, 3205294SN/A MISCREG_HS_BASE, 3215294SN/A MISCREG_TSL_BASE, 3225294SN/A MISCREG_TSG_BASE, 3235294SN/A MISCREG_LS_BASE, 3245294SN/A MISCREG_MS_BASE, 3255294SN/A MISCREG_TR_BASE, 3265294SN/A MISCREG_IDTR_BASE, 3274700SN/A 3285289SN/A // The effective segment base, ie what is actually added to an 3295289SN/A // address. In 64 bit mode this can be different from the above, 3305289SN/A // namely 0. 3315294SN/A MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 3325289SN/A MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 3335289SN/A MISCREG_CS_EFF_BASE, 3345289SN/A MISCREG_SS_EFF_BASE, 3355289SN/A MISCREG_DS_EFF_BASE, 3365289SN/A MISCREG_FS_EFF_BASE, 3375289SN/A MISCREG_GS_EFF_BASE, 3385294SN/A MISCREG_HS_EFF_BASE, 3395294SN/A MISCREG_TSL_EFF_BASE, 3405294SN/A MISCREG_TSG_EFF_BASE, 3415294SN/A MISCREG_LS_EFF_BASE, 3425294SN/A MISCREG_MS_EFF_BASE, 3435294SN/A MISCREG_TR_EFF_BASE, 3445294SN/A MISCREG_IDTR_EFF_BASE, 3455289SN/A 3464700SN/A // Hidden segment limit field 3475294SN/A MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 3484862SN/A MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 3494700SN/A MISCREG_CS_LIMIT, 3504700SN/A MISCREG_SS_LIMIT, 3514700SN/A MISCREG_DS_LIMIT, 3524700SN/A MISCREG_FS_LIMIT, 3534700SN/A MISCREG_GS_LIMIT, 3545294SN/A MISCREG_HS_LIMIT, 3555294SN/A MISCREG_TSL_LIMIT, 3565294SN/A MISCREG_TSG_LIMIT, 3575294SN/A MISCREG_LS_LIMIT, 3585294SN/A MISCREG_MS_LIMIT, 3595294SN/A MISCREG_TR_LIMIT, 3605294SN/A MISCREG_IDTR_LIMIT, 3614700SN/A 3624700SN/A // Hidden segment limit attributes 3635294SN/A MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 3644862SN/A MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 3654700SN/A MISCREG_CS_ATTR, 3664700SN/A MISCREG_SS_ATTR, 3674700SN/A MISCREG_DS_ATTR, 3684700SN/A MISCREG_FS_ATTR, 3694700SN/A MISCREG_GS_ATTR, 3705294SN/A MISCREG_HS_ATTR, 3715294SN/A MISCREG_TSL_ATTR, 3725294SN/A MISCREG_TSG_ATTR, 3735294SN/A MISCREG_LS_ATTR, 3745294SN/A MISCREG_MS_ATTR, 3754700SN/A MISCREG_TR_ATTR, 3765294SN/A MISCREG_IDTR_ATTR, 3774700SN/A 3785082SN/A // Floating point control registers 3795294SN/A MISCREG_X87_TOP = 3805294SN/A MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 3815082SN/A 3826362SN/A MISCREG_MXCSR, 3836362SN/A MISCREG_FCW, 3846362SN/A MISCREG_FSW, 3856362SN/A MISCREG_FTW, 3866362SN/A MISCREG_FTAG, 3876362SN/A MISCREG_FISEG, 3886362SN/A MISCREG_FIOFF, 3896362SN/A MISCREG_FOSEG, 3906362SN/A MISCREG_FOOFF, 3916362SN/A MISCREG_FOP, 3926362SN/A 3934700SN/A //XXX Add "Model-Specific Registers" 3944700SN/A 3955360SN/A MISCREG_APIC_BASE, 3965360SN/A 3975360SN/A // "Fake" MSRs for internally implemented devices 3985357SN/A MISCREG_PCI_CONFIG_ADDRESS, 3995357SN/A 4005082SN/A NUM_MISCREGS 4014700SN/A }; 4024700SN/A 40311324Ssteve.reinhardt@amd.com static inline bool 40411324Ssteve.reinhardt@amd.com isValidMiscReg(int index) 40511324Ssteve.reinhardt@amd.com { 40611324Ssteve.reinhardt@amd.com return (index >= MISCREG_CR0 && index < NUM_MISCREGS && 40711324Ssteve.reinhardt@amd.com index != MISCREG_CR1 && 40811324Ssteve.reinhardt@amd.com !(index > MISCREG_CR4 && index < MISCREG_CR8) && 40911324Ssteve.reinhardt@amd.com !(index > MISCREG_CR8 && index <= MISCREG_CR15)); 41011324Ssteve.reinhardt@amd.com } 41111324Ssteve.reinhardt@amd.com 4125025SN/A static inline MiscRegIndex 4135025SN/A MISCREG_CR(int index) 4145025SN/A { 4156346SN/A assert(index >= 0 && index < NumCRegs); 4165025SN/A return (MiscRegIndex)(MISCREG_CR_BASE + index); 4175025SN/A } 4185025SN/A 4195025SN/A static inline MiscRegIndex 4205025SN/A MISCREG_DR(int index) 4215025SN/A { 4226346SN/A assert(index >= 0 && index < NumDRegs); 4235025SN/A return (MiscRegIndex)(MISCREG_DR_BASE + index); 4245025SN/A } 4255025SN/A 4265025SN/A static inline MiscRegIndex 4275138SN/A MISCREG_MTRR_PHYS_BASE(int index) 4285138SN/A { 4296346SN/A assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - 4306346SN/A MISCREG_MTRR_PHYS_BASE_BASE)); 4315138SN/A return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 4325138SN/A } 4335138SN/A 4345138SN/A static inline MiscRegIndex 4355138SN/A MISCREG_MTRR_PHYS_MASK(int index) 4365138SN/A { 4376346SN/A assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - 4386346SN/A MISCREG_MTRR_PHYS_MASK_BASE)); 4395138SN/A return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 4405138SN/A } 4415138SN/A 4425138SN/A static inline MiscRegIndex 4435138SN/A MISCREG_MC_CTL(int index) 4445138SN/A { 4456346SN/A assert(index >= 0 && index < (MISCREG_MC_CTL_END - 4466346SN/A MISCREG_MC_CTL_BASE)); 4475138SN/A return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 4485138SN/A } 4495138SN/A 4505138SN/A static inline MiscRegIndex 4515138SN/A MISCREG_MC_STATUS(int index) 4525138SN/A { 4536346SN/A assert(index >= 0 && index < (MISCREG_MC_STATUS_END - 4546346SN/A MISCREG_MC_STATUS_BASE)); 4555138SN/A return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 4565138SN/A } 4575138SN/A 4585138SN/A static inline MiscRegIndex 4595138SN/A MISCREG_MC_ADDR(int index) 4605138SN/A { 4616346SN/A assert(index >= 0 && index < (MISCREG_MC_ADDR_END - 4626346SN/A MISCREG_MC_ADDR_BASE)); 4635138SN/A return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 4645138SN/A } 4655138SN/A 4665138SN/A static inline MiscRegIndex 4675138SN/A MISCREG_MC_MISC(int index) 4685138SN/A { 4696346SN/A assert(index >= 0 && index < (MISCREG_MC_MISC_END - 4706346SN/A MISCREG_MC_MISC_BASE)); 4715138SN/A return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 4725138SN/A } 4735138SN/A 4745138SN/A static inline MiscRegIndex 4755138SN/A MISCREG_PERF_EVT_SEL(int index) 4765138SN/A { 4776346SN/A assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - 4786346SN/A MISCREG_PERF_EVT_SEL_BASE)); 4795138SN/A return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 4805138SN/A } 4815138SN/A 4825138SN/A static inline MiscRegIndex 4835138SN/A MISCREG_PERF_EVT_CTR(int index) 4845138SN/A { 4856346SN/A assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - 4866346SN/A MISCREG_PERF_EVT_CTR_BASE)); 4875138SN/A return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 4885138SN/A } 4895138SN/A 4905138SN/A static inline MiscRegIndex 4915138SN/A MISCREG_IORR_BASE(int index) 4925138SN/A { 4936346SN/A assert(index >= 0 && index < (MISCREG_IORR_BASE_END - 4946346SN/A MISCREG_IORR_BASE_BASE)); 4955138SN/A return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 4965138SN/A } 4975138SN/A 4985138SN/A static inline MiscRegIndex 4995138SN/A MISCREG_IORR_MASK(int index) 5005138SN/A { 5016346SN/A assert(index >= 0 && index < (MISCREG_IORR_MASK_END - 5026346SN/A MISCREG_IORR_MASK_BASE)); 5035138SN/A return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 5045138SN/A } 5055138SN/A 5065138SN/A static inline MiscRegIndex 5075025SN/A MISCREG_SEG_SEL(int index) 5085025SN/A { 5096346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5105025SN/A return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 5115025SN/A } 5125025SN/A 5135025SN/A static inline MiscRegIndex 5145025SN/A MISCREG_SEG_BASE(int index) 5155025SN/A { 5166346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5175025SN/A return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 5185025SN/A } 5195025SN/A 5205025SN/A static inline MiscRegIndex 5215289SN/A MISCREG_SEG_EFF_BASE(int index) 5225289SN/A { 5236346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5245289SN/A return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 5255289SN/A } 5265289SN/A 5275289SN/A static inline MiscRegIndex 5285025SN/A MISCREG_SEG_LIMIT(int index) 5295025SN/A { 5306346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5315025SN/A return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 5325025SN/A } 5335025SN/A 5345025SN/A static inline MiscRegIndex 5355025SN/A MISCREG_SEG_ATTR(int index) 5365025SN/A { 5376346SN/A assert(index >= 0 && index < NUM_SEGMENTREGS); 5385025SN/A return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 5395025SN/A } 5405025SN/A 5414700SN/A /** 5424700SN/A * A type to describe the condition code bits of the RFLAGS register, 5434700SN/A * plus two flags, EZF and ECF, which are only visible to microcode. 5444700SN/A */ 5454684SN/A BitUnion64(CCFlagBits) 5465138SN/A Bitfield<11> of; 5475138SN/A Bitfield<7> sf; 5485138SN/A Bitfield<6> zf; 5495138SN/A Bitfield<5> ezf; 5505138SN/A Bitfield<4> af; 5515138SN/A Bitfield<3> ecf; 5525138SN/A Bitfield<2> pf; 5535138SN/A Bitfield<0> cf; 5544684SN/A EndBitUnion(CCFlagBits) 5554700SN/A 5564700SN/A /** 5574700SN/A * RFLAGS 5584700SN/A */ 5594700SN/A BitUnion64(RFLAGS) 5605138SN/A Bitfield<21> id; // ID Flag 5615138SN/A Bitfield<20> vip; // Virtual Interrupt Pending 5625138SN/A Bitfield<19> vif; // Virtual Interrupt Flag 5635138SN/A Bitfield<18> ac; // Alignment Check 5645138SN/A Bitfield<17> vm; // Virtual-8086 Mode 5655138SN/A Bitfield<16> rf; // Resume Flag 5665138SN/A Bitfield<14> nt; // Nested Task 5675138SN/A Bitfield<13, 12> iopl; // I/O Privilege Level 5685138SN/A Bitfield<11> of; // Overflow Flag 5695138SN/A Bitfield<10> df; // Direction Flag 5705138SN/A Bitfield<9> intf; // Interrupt Flag 5715138SN/A Bitfield<8> tf; // Trap Flag 5725138SN/A Bitfield<7> sf; // Sign Flag 5735138SN/A Bitfield<6> zf; // Zero Flag 5745138SN/A Bitfield<4> af; // Auxiliary Flag 5755138SN/A Bitfield<2> pf; // Parity Flag 5765138SN/A Bitfield<0> cf; // Carry Flag 5774700SN/A EndBitUnion(RFLAGS) 5784700SN/A 5795429SN/A BitUnion64(HandyM5Reg) 5805429SN/A Bitfield<0> mode; 5815429SN/A Bitfield<3, 1> submode; 5825429SN/A Bitfield<5, 4> cpl; 5836141SN/A Bitfield<6> paging; 5846141SN/A Bitfield<7> prot; 5856142SN/A Bitfield<9, 8> defOp; 5866142SN/A Bitfield<11, 10> altOp; 5876142SN/A Bitfield<13, 12> defAddr; 5886142SN/A Bitfield<15, 14> altAddr; 5896142SN/A Bitfield<17, 16> stack; 5905429SN/A EndBitUnion(HandyM5Reg) 5915429SN/A 5924700SN/A /** 5934700SN/A * Control registers 5944700SN/A */ 5954700SN/A BitUnion64(CR0) 5965138SN/A Bitfield<31> pg; // Paging 5975138SN/A Bitfield<30> cd; // Cache Disable 5985138SN/A Bitfield<29> nw; // Not Writethrough 5995138SN/A Bitfield<18> am; // Alignment Mask 6005138SN/A Bitfield<16> wp; // Write Protect 6015138SN/A Bitfield<5> ne; // Numeric Error 6025138SN/A Bitfield<4> et; // Extension Type 6035138SN/A Bitfield<3> ts; // Task Switched 6045138SN/A Bitfield<2> em; // Emulation 6055138SN/A Bitfield<1> mp; // Monitor Coprocessor 6065138SN/A Bitfield<0> pe; // Protection Enabled 6074700SN/A EndBitUnion(CR0) 6084700SN/A 6094700SN/A // Page Fault Virtual Address 6104700SN/A BitUnion64(CR2) 6114700SN/A Bitfield<31, 0> legacy; 6124700SN/A EndBitUnion(CR2) 6134700SN/A 6144700SN/A BitUnion64(CR3) 6155138SN/A Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 6164700SN/A // Base Address 6175138SN/A Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 6184700SN/A // Base Address 6195138SN/A Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 6204700SN/A // Base Address 6215138SN/A Bitfield<4> pcd; // Page-Level Cache Disable 6225138SN/A Bitfield<3> pwt; // Page-Level Writethrough 6234700SN/A EndBitUnion(CR3) 6244700SN/A 6254700SN/A BitUnion64(CR4) 62610554Salexandru.dutu@amd.com Bitfield<18> osxsave; // Enable XSAVE and Proc Extended States 62710554Salexandru.dutu@amd.com Bitfield<16> fsgsbase; // Enable RDFSBASE, RDGSBASE, WRFSBASE, 62810554Salexandru.dutu@amd.com // WRGSBASE instructions 6295138SN/A Bitfield<10> osxmmexcpt; // Operating System Unmasked 6304700SN/A // Exception Support 6315138SN/A Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 6325138SN/A Bitfield<8> pce; // Performance-Monitoring Counter Enable 6335138SN/A Bitfield<7> pge; // Page-Global Enable 6345138SN/A Bitfield<6> mce; // Machine Check Enable 6355138SN/A Bitfield<5> pae; // Physical-Address Extension 6365138SN/A Bitfield<4> pse; // Page Size Extensions 6375138SN/A Bitfield<3> de; // Debugging Extensions 6385138SN/A Bitfield<2> tsd; // Time Stamp Disable 6395138SN/A Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 6405138SN/A Bitfield<0> vme; // Virtual-8086 Mode Extensions 6414700SN/A EndBitUnion(CR4) 6424700SN/A 6434700SN/A BitUnion64(CR8) 6445138SN/A Bitfield<3, 0> tpr; // Task Priority Register 6455138SN/A EndBitUnion(CR8) 6465138SN/A 6475925SN/A BitUnion64(DR6) 6485925SN/A Bitfield<0> b0; 6495925SN/A Bitfield<1> b1; 6505925SN/A Bitfield<2> b2; 6515925SN/A Bitfield<3> b3; 6525925SN/A Bitfield<13> bd; 6535925SN/A Bitfield<14> bs; 6545925SN/A Bitfield<15> bt; 6555925SN/A EndBitUnion(DR6) 6565925SN/A 6575925SN/A BitUnion64(DR7) 6585925SN/A Bitfield<0> l0; 6595925SN/A Bitfield<1> g0; 6605925SN/A Bitfield<2> l1; 6615925SN/A Bitfield<3> g1; 6625925SN/A Bitfield<4> l2; 6635925SN/A Bitfield<5> g2; 6645925SN/A Bitfield<6> l3; 6655925SN/A Bitfield<7> g3; 6665925SN/A Bitfield<8> le; 6675925SN/A Bitfield<9> ge; 6685925SN/A Bitfield<13> gd; 6695925SN/A Bitfield<17, 16> rw0; 6705925SN/A Bitfield<19, 18> len0; 6715925SN/A Bitfield<21, 20> rw1; 6725925SN/A Bitfield<23, 22> len1; 6735925SN/A Bitfield<25, 24> rw2; 6745925SN/A Bitfield<27, 26> len2; 6755925SN/A Bitfield<29, 28> rw3; 6765925SN/A Bitfield<31, 30> len3; 6775925SN/A EndBitUnion(DR7) 6785925SN/A 6795138SN/A // MTRR capabilities 6805138SN/A BitUnion64(MTRRcap) 6815138SN/A Bitfield<7, 0> vcnt; // Variable-Range Register Count 6825138SN/A Bitfield<8> fix; // Fixed-Range Registers 6835138SN/A Bitfield<10> wc; // Write-Combining 6845138SN/A EndBitUnion(MTRRcap) 6855138SN/A 6865138SN/A /** 6875138SN/A * SYSENTER configuration registers 6885138SN/A */ 6895138SN/A BitUnion64(SysenterCS) 6905138SN/A Bitfield<15, 0> targetCS; 6915138SN/A EndBitUnion(SysenterCS) 6925138SN/A 6935138SN/A BitUnion64(SysenterESP) 6945138SN/A Bitfield<31, 0> targetESP; 6955138SN/A EndBitUnion(SysenterESP) 6965138SN/A 6975138SN/A BitUnion64(SysenterEIP) 6985138SN/A Bitfield<31, 0> targetEIP; 6995138SN/A EndBitUnion(SysenterEIP) 7005138SN/A 7015138SN/A /** 7025138SN/A * Global machine check registers 7035138SN/A */ 7045138SN/A BitUnion64(McgCap) 7055138SN/A Bitfield<7, 0> count; // Number of error reporting register banks 7065138SN/A Bitfield<8> MCGCP; // MCG_CTL register present. 7075138SN/A EndBitUnion(McgCap) 7085138SN/A 7095138SN/A BitUnion64(McgStatus) 7105138SN/A Bitfield<0> ripv; // Restart-IP valid 7115138SN/A Bitfield<1> eipv; // Error-IP valid 7125138SN/A Bitfield<2> mcip; // Machine check in-progress 7135138SN/A EndBitUnion(McgStatus) 7145138SN/A 7155138SN/A BitUnion64(DebugCtlMsr) 7165138SN/A Bitfield<0> lbr; // Last-branch record 7175138SN/A Bitfield<1> btf; // Branch single step 7185138SN/A Bitfield<2> pb0; // Performance monitoring pin control 0 7195138SN/A Bitfield<3> pb1; // Performance monitoring pin control 1 7205138SN/A Bitfield<4> pb2; // Performance monitoring pin control 2 7215138SN/A Bitfield<5> pb3; // Performance monitoring pin control 3 7225138SN/A /*uint64_t pb(int index) 7235138SN/A { 7245138SN/A return bits(__data, index + 2); 7255138SN/A }*/ 7265138SN/A EndBitUnion(DebugCtlMsr) 7275138SN/A 7285138SN/A BitUnion64(MtrrPhysBase) 7295138SN/A Bitfield<7, 0> type; // Default memory type 7305138SN/A Bitfield<51, 12> physbase; // Range physical base address 7315138SN/A EndBitUnion(MtrrPhysBase) 7325138SN/A 7335138SN/A BitUnion64(MtrrPhysMask) 7345138SN/A Bitfield<11> valid; // MTRR pair enable 7355138SN/A Bitfield<51, 12> physmask; // Range physical mask 7365138SN/A EndBitUnion(MtrrPhysMask) 7375138SN/A 7385138SN/A BitUnion64(MtrrFixed) 7395138SN/A /*uint64_t type(int index) 7405138SN/A { 7415138SN/A return bits(__data, index * 8 + 7, index * 8); 7425138SN/A }*/ 7435138SN/A EndBitUnion(MtrrFixed) 7445138SN/A 7455138SN/A BitUnion64(Pat) 7465138SN/A /*uint64_t pa(int index) 7475138SN/A { 7485138SN/A return bits(__data, index * 8 + 2, index * 8); 7495138SN/A }*/ 7505138SN/A EndBitUnion(Pat) 7515138SN/A 7525138SN/A BitUnion64(MtrrDefType) 7535138SN/A Bitfield<7, 0> type; // Default type 7545138SN/A Bitfield<10> fe; // Fixed range enable 7555138SN/A Bitfield<11> e; // MTRR enable 7565138SN/A EndBitUnion(MtrrDefType) 7575138SN/A 7585138SN/A /** 7595138SN/A * Machine check 7605138SN/A */ 7615138SN/A BitUnion64(McStatus) 7625138SN/A Bitfield<15,0> mcaErrorCode; 7635138SN/A Bitfield<31,16> modelSpecificCode; 7645138SN/A Bitfield<56,32> otherInfo; 7655138SN/A Bitfield<57> pcc; // Processor-context corrupt 7665138SN/A Bitfield<58> addrv; // Error-address register valid 7675138SN/A Bitfield<59> miscv; // Miscellaneous-error register valid 7685138SN/A Bitfield<60> en; // Error condition enabled 7695138SN/A Bitfield<61> uc; // Uncorrected error 7705138SN/A Bitfield<62> over; // Status register overflow 7715138SN/A Bitfield<63> val; // Valid 7725138SN/A EndBitUnion(McStatus) 7735138SN/A 7745138SN/A BitUnion64(McCtl) 7755138SN/A /*uint64_t en(int index) 7765138SN/A { 7775138SN/A return bits(__data, index); 7785138SN/A }*/ 7795138SN/A EndBitUnion(McCtl) 7805138SN/A 7815138SN/A // Extended feature enable register 7825138SN/A BitUnion64(Efer) 7835138SN/A Bitfield<0> sce; // System call extensions 7845138SN/A Bitfield<8> lme; // Long mode enable 7855138SN/A Bitfield<10> lma; // Long mode active 7865138SN/A Bitfield<11> nxe; // No-execute enable 7875138SN/A Bitfield<12> svme; // Secure virtual machine enable 7885138SN/A Bitfield<14> ffxsr; // Fast fxsave/fxrstor 7895138SN/A EndBitUnion(Efer) 7905138SN/A 7915138SN/A BitUnion64(Star) 7925138SN/A Bitfield<31,0> targetEip; 7935138SN/A Bitfield<47,32> syscallCsAndSs; 7945138SN/A Bitfield<63,48> sysretCsAndSs; 7955138SN/A EndBitUnion(Star) 7965138SN/A 7975138SN/A BitUnion64(SfMask) 7985138SN/A Bitfield<31,0> mask; 7995138SN/A EndBitUnion(SfMask) 8005138SN/A 8015138SN/A BitUnion64(PerfEvtSel) 8025138SN/A Bitfield<7,0> eventMask; 8035138SN/A Bitfield<15,8> unitMask; 8045138SN/A Bitfield<16> usr; // User mode 8055138SN/A Bitfield<17> os; // Operating-system mode 8065138SN/A Bitfield<18> e; // Edge detect 8075138SN/A Bitfield<19> pc; // Pin control 8085138SN/A Bitfield<20> intEn; // Interrupt enable 8095138SN/A Bitfield<22> en; // Counter enable 8105138SN/A Bitfield<23> inv; // Invert mask 8115138SN/A Bitfield<31,24> counterMask; 8125138SN/A EndBitUnion(PerfEvtSel) 8135138SN/A 8145138SN/A BitUnion32(Syscfg) 8155138SN/A Bitfield<18> mfde; // MtrrFixDramEn 8165138SN/A Bitfield<19> mfdm; // MtrrFixDramModEn 8175138SN/A Bitfield<20> mvdm; // MtrrVarDramEn 8185138SN/A Bitfield<21> tom2; // MtrrTom2En 8195138SN/A EndBitUnion(Syscfg) 8205138SN/A 8215138SN/A BitUnion64(IorrBase) 8225138SN/A Bitfield<3> wr; // WrMem Enable 8235138SN/A Bitfield<4> rd; // RdMem Enable 8245138SN/A Bitfield<51,12> physbase; // Range physical base address 8255138SN/A EndBitUnion(IorrBase) 8265138SN/A 8275138SN/A BitUnion64(IorrMask) 8285138SN/A Bitfield<11> v; // I/O register pair enable (valid) 8295138SN/A Bitfield<51,12> physmask; // Range physical mask 8305138SN/A EndBitUnion(IorrMask) 8315138SN/A 8325138SN/A BitUnion64(Tom) 8335138SN/A Bitfield<51,23> physAddr; // Top of memory physical address 8345138SN/A EndBitUnion(Tom) 8355138SN/A 8365138SN/A BitUnion64(VmCrMsr) 8375138SN/A Bitfield<0> dpd; 8385138SN/A Bitfield<1> rInit; 8395138SN/A Bitfield<2> disA20M; 8405138SN/A EndBitUnion(VmCrMsr) 8415138SN/A 8425138SN/A BitUnion64(IgnneMsr) 8435138SN/A Bitfield<0> ignne; 8445138SN/A EndBitUnion(IgnneMsr) 8455138SN/A 8465138SN/A BitUnion64(SmmCtlMsr) 8475138SN/A Bitfield<0> dismiss; 8485138SN/A Bitfield<1> enter; 8495138SN/A Bitfield<2> smiCycle; 8505138SN/A Bitfield<3> exit; 8515138SN/A Bitfield<4> rsmCycle; 8525138SN/A EndBitUnion(SmmCtlMsr) 8534700SN/A 8544700SN/A /** 8554700SN/A * Segment Selector 8564700SN/A */ 8574700SN/A BitUnion64(SegSelector) 8585294SN/A // The following bitfield is not defined in the ISA, but it's useful 8595294SN/A // when checking selectors in larger data types to make sure they 8605294SN/A // aren't too large. 8615294SN/A Bitfield<63, 3> esi; // Extended selector 8625138SN/A Bitfield<15, 3> si; // Selector Index 8635138SN/A Bitfield<2> ti; // Table Indicator 8645138SN/A Bitfield<1, 0> rpl; // Requestor Privilege Level 8654700SN/A EndBitUnion(SegSelector) 8664700SN/A 8674700SN/A /** 8684700SN/A * Segment Descriptors 8694700SN/A */ 8704700SN/A 87112588Sgabeblack@google.com class SegDescriptorBase 87212588Sgabeblack@google.com { 87312588Sgabeblack@google.com public: 87412588Sgabeblack@google.com uint32_t 87512588Sgabeblack@google.com getter(const uint64_t &storage) const 87612588Sgabeblack@google.com { 87712588Sgabeblack@google.com return (bits(storage, 63, 56) << 24) | bits(storage, 39, 16); 87812588Sgabeblack@google.com } 87912588Sgabeblack@google.com 88012588Sgabeblack@google.com void 88112588Sgabeblack@google.com setter(uint64_t &storage, uint32_t base) 88212588Sgabeblack@google.com { 88312588Sgabeblack@google.com replaceBits(storage, 63, 56, bits(base, 31, 24)); 88412588Sgabeblack@google.com replaceBits(storage, 39, 16, bits(base, 23, 0)); 88512588Sgabeblack@google.com } 88612588Sgabeblack@google.com }; 88712588Sgabeblack@google.com 88812588Sgabeblack@google.com class SegDescriptorLimit 88912588Sgabeblack@google.com { 89012588Sgabeblack@google.com public: 89112588Sgabeblack@google.com uint32_t 89212588Sgabeblack@google.com getter(const uint64_t &storage) const 89312588Sgabeblack@google.com { 89412588Sgabeblack@google.com uint32_t limit = (bits(storage, 51, 48) << 16) | 89512588Sgabeblack@google.com bits(storage, 15, 0); 89612588Sgabeblack@google.com if (bits(storage, 55)) 89712588Sgabeblack@google.com limit = (limit << 12) | mask(12); 89812588Sgabeblack@google.com return limit; 89912588Sgabeblack@google.com } 90012588Sgabeblack@google.com 90112588Sgabeblack@google.com void 90212588Sgabeblack@google.com setter(uint64_t &storage, uint32_t limit) 90312588Sgabeblack@google.com { 90412588Sgabeblack@google.com bool g = (bits(limit, 31, 24) != 0); 90512588Sgabeblack@google.com panic_if(g && bits(limit, 11, 0) != mask(12), 90612588Sgabeblack@google.com "Inlimitid segment limit %#x", limit); 90712588Sgabeblack@google.com if (g) 90812588Sgabeblack@google.com limit = limit >> 12; 90912588Sgabeblack@google.com replaceBits(storage, 51, 48, bits(limit, 23, 16)); 91012588Sgabeblack@google.com replaceBits(storage, 15, 0, bits(limit, 15, 0)); 91112588Sgabeblack@google.com replaceBits(storage, 55, g ? 1 : 0); 91212588Sgabeblack@google.com } 91312588Sgabeblack@google.com }; 91412588Sgabeblack@google.com 9154700SN/A BitUnion64(SegDescriptor) 9164700SN/A Bitfield<63, 56> baseHigh; 9174700SN/A Bitfield<39, 16> baseLow; 91812588Sgabeblack@google.com BitfieldType<SegDescriptorBase> base; 9195138SN/A Bitfield<55> g; // Granularity 9205138SN/A Bitfield<54> d; // Default Operand Size 9215138SN/A Bitfield<54> b; // Default Operand Size 9225138SN/A Bitfield<53> l; // Long Attribute Bit 9235138SN/A Bitfield<52> avl; // Available To Software 9244700SN/A Bitfield<51, 48> limitHigh; 9254700SN/A Bitfield<15, 0> limitLow; 92612588Sgabeblack@google.com BitfieldType<SegDescriptorLimit> limit; 9275138SN/A Bitfield<47> p; // Present 9285138SN/A Bitfield<46, 45> dpl; // Descriptor Privilege-Level 9295138SN/A Bitfield<44> s; // System 9304700SN/A SubBitUnion(type, 43, 40) 9314700SN/A // Specifies whether this descriptor is for code or data. 9324700SN/A Bitfield<43> codeOrData; 9334700SN/A 9344700SN/A // These bit fields are for code segments 9355138SN/A Bitfield<42> c; // Conforming 9365138SN/A Bitfield<41> r; // Readable 9374700SN/A 9384700SN/A // These bit fields are for data segments 9395138SN/A Bitfield<42> e; // Expand-Down 9405138SN/A Bitfield<41> w; // Writable 9414700SN/A 9424700SN/A // This is used for both code and data segments. 9435138SN/A Bitfield<40> a; // Accessed 9444700SN/A EndSubBitUnion(type) 9454700SN/A EndBitUnion(SegDescriptor) 9464700SN/A 94710554Salexandru.dutu@amd.com /** 94810554Salexandru.dutu@amd.com * TSS Descriptor (long mode - 128 bits) 94910554Salexandru.dutu@amd.com * the lower 64 bits 95010554Salexandru.dutu@amd.com */ 95110554Salexandru.dutu@amd.com BitUnion64(TSSlow) 95210554Salexandru.dutu@amd.com Bitfield<63, 56> baseHigh; 95310554Salexandru.dutu@amd.com Bitfield<39, 16> baseLow; 95412588Sgabeblack@google.com BitfieldType<SegDescriptorBase> base; 95510554Salexandru.dutu@amd.com Bitfield<55> g; // Granularity 95610554Salexandru.dutu@amd.com Bitfield<52> avl; // Available To Software 95710554Salexandru.dutu@amd.com Bitfield<51, 48> limitHigh; 95810554Salexandru.dutu@amd.com Bitfield<15, 0> limitLow; 95912588Sgabeblack@google.com BitfieldType<SegDescriptorLimit> limit; 96010554Salexandru.dutu@amd.com Bitfield<47> p; // Present 96110554Salexandru.dutu@amd.com Bitfield<46, 45> dpl; // Descriptor Privilege-Level 96210554Salexandru.dutu@amd.com SubBitUnion(type, 43, 40) 96310554Salexandru.dutu@amd.com // Specifies whether this descriptor is for code or data. 96410554Salexandru.dutu@amd.com Bitfield<43> codeOrData; 96510554Salexandru.dutu@amd.com 96610554Salexandru.dutu@amd.com // These bit fields are for code segments 96710554Salexandru.dutu@amd.com Bitfield<42> c; // Conforming 96810554Salexandru.dutu@amd.com Bitfield<41> r; // Readable 96910554Salexandru.dutu@amd.com 97010554Salexandru.dutu@amd.com // These bit fields are for data segments 97110554Salexandru.dutu@amd.com Bitfield<42> e; // Expand-Down 97210554Salexandru.dutu@amd.com Bitfield<41> w; // Writable 97310554Salexandru.dutu@amd.com 97410554Salexandru.dutu@amd.com // This is used for both code and data segments. 97510554Salexandru.dutu@amd.com Bitfield<40> a; // Accessed 97610554Salexandru.dutu@amd.com EndSubBitUnion(type) 97710554Salexandru.dutu@amd.com EndBitUnion(TSSlow) 97810554Salexandru.dutu@amd.com 97910554Salexandru.dutu@amd.com /** 98010554Salexandru.dutu@amd.com * TSS Descriptor (long mode - 128 bits) 98110554Salexandru.dutu@amd.com * the upper 64 bits 98210554Salexandru.dutu@amd.com */ 98310554Salexandru.dutu@amd.com BitUnion64(TSShigh) 98410554Salexandru.dutu@amd.com Bitfield<31, 0> base; 98510554Salexandru.dutu@amd.com EndBitUnion(TSShigh) 98610554Salexandru.dutu@amd.com 9875138SN/A BitUnion64(SegAttr) 9886222SN/A Bitfield<1, 0> dpl; 9896222SN/A Bitfield<2> unusable; 9906222SN/A Bitfield<3> defaultSize; 9916222SN/A Bitfield<4> longMode; 9926222SN/A Bitfield<5> avl; 9936222SN/A Bitfield<6> granularity; 9946222SN/A Bitfield<7> present; 9956222SN/A Bitfield<11, 8> type; 9966222SN/A Bitfield<12> writable; 9976222SN/A Bitfield<13> readable; 9986222SN/A Bitfield<14> expandDown; 9996222SN/A Bitfield<15> system; 10005138SN/A EndBitUnion(SegAttr) 10015138SN/A 10024700SN/A BitUnion64(GateDescriptor) 10034700SN/A Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 10044700SN/A Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 10054700SN/A Bitfield<31, 16> selector; // Target Code-Segment Selector 10065138SN/A Bitfield<47> p; // Present 10075138SN/A Bitfield<46, 45> dpl; // Descriptor Privilege-Level 10084700SN/A Bitfield<43, 40> type; 10094700SN/A Bitfield<36, 32> count; // Parameter Count 10104700SN/A EndBitUnion(GateDescriptor) 10114700SN/A 10124700SN/A /** 101310554Salexandru.dutu@amd.com * Long Mode Gate Descriptor 101410554Salexandru.dutu@amd.com */ 101510554Salexandru.dutu@amd.com BitUnion64(GateDescriptorLow) 101610554Salexandru.dutu@amd.com Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 101710554Salexandru.dutu@amd.com Bitfield<47> p; // Present 101810554Salexandru.dutu@amd.com Bitfield<46, 45> dpl; // Descriptor Privilege-Level 101910554Salexandru.dutu@amd.com Bitfield<43, 40> type; 102010554Salexandru.dutu@amd.com Bitfield<35, 32> IST; // IST pointer to TSS -- new stack for exception handling 102110554Salexandru.dutu@amd.com Bitfield<31, 16> selector; // Target Code-Segment Selector 102210554Salexandru.dutu@amd.com Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 102310554Salexandru.dutu@amd.com EndBitUnion(GateDescriptorLow) 102410554Salexandru.dutu@amd.com 102510554Salexandru.dutu@amd.com BitUnion64(GateDescriptorHigh) 102610554Salexandru.dutu@amd.com Bitfield<31, 0> offset; // Target Code-Segment Offset 102710554Salexandru.dutu@amd.com EndBitUnion(GateDescriptorHigh) 102810554Salexandru.dutu@amd.com 102910554Salexandru.dutu@amd.com /** 10304700SN/A * Descriptor-Table Registers 10314700SN/A */ 10324700SN/A BitUnion64(GDTR) 10334700SN/A EndBitUnion(GDTR) 10344700SN/A 10354700SN/A BitUnion64(IDTR) 10364700SN/A EndBitUnion(IDTR) 10374700SN/A 10384700SN/A BitUnion64(LDTR) 10394700SN/A EndBitUnion(LDTR) 10404700SN/A 10414700SN/A /** 10424700SN/A * Task Register 10434700SN/A */ 10444700SN/A BitUnion64(TR) 10454700SN/A EndBitUnion(TR) 10465360SN/A 10475360SN/A 10485360SN/A /** 10495360SN/A * Local APIC Base Register 10505360SN/A */ 10515360SN/A BitUnion64(LocalApicBase) 10525360SN/A Bitfield<51, 12> base; 10535360SN/A Bitfield<11> enable; 10545360SN/A Bitfield<8> bsp; 10555360SN/A EndBitUnion(LocalApicBase) 10568902Sandreas.hansson@arm.com} 10574684SN/A 10584684SN/A#endif // __ARCH_X86_INTREGS_HH__ 1059