Searched refs:objects (Results 101 - 125 of 312) sorted by relevance
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/gem5/src/mem/ruby/system/ |
H A D | WeightedLRUReplacementPolicy.py | 36 from m5.objects.ReplacementPolicy import ReplacementPolicy
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/gem5/src/arch/arm/ |
H A D | ArmSemihosting.py | 41 from m5.objects.Serial import SerialDevice 42 from m5.objects.Terminal import Terminal
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/gem5/src/arch/x86/ |
H A D | X86TLB.py | 41 from m5.objects.BaseTLB import BaseTLB 42 from m5.objects.ClockedObject import ClockedObject
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H A D | X86LocalApic.py | 45 from m5.objects.Device import PioDevice 46 from m5.objects.ClockDomain import DerivedClockDomain
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/gem5/src/cpu/ |
H A D | BaseCPU.py | 55 from m5.objects.ClockedObject import ClockedObject 56 from m5.objects.XBar import L2XBar 57 from m5.objects.InstTracer import InstTracer 58 from m5.objects.CPUTracers import ExeTracer 59 from m5.objects.SubSystem import SubSystem 60 from m5.objects.ClockDomain import * 61 from m5.objects.Platform import Platform 66 from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB 67 from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts 68 from m5.objects [all...] |
H A D | CheckerCPU.py | 31 from m5.objects.BaseCPU import BaseCPU
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/gem5/configs/common/ |
H A D | CpuConfig.py | 42 import m5.objects 57 return issubclass(cls, m5.objects.BaseCPU) and \ 59 not issubclass(cls, m5.objects.CheckerCPU) 64 cpu_class = getattr(m5.objects, name, None) 106 if issubclass(cpu_cls, m5.objects.DerivO3CPU): 113 cpu.traceListener = m5.objects.ElasticTrace( 130 for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
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H A D | BPConfig.py | 36 import m5.objects 51 return issubclass(cls, m5.objects.BranchPredictor) and \ 86 for name, cls in inspect.getmembers(m5.objects, is_bp_class): 102 return issubclass(cls, m5.objects.IndirectPredictor) and \ 137 for name, cls in inspect.getmembers(m5.objects, is_indirect_bp_class):
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H A D | HWPConfig.py | 36 import m5.objects 51 return issubclass(cls, m5.objects.BasePrefetcher) and \ 86 for name, cls in inspect.getmembers(m5.objects, is_hwp_class):
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/gem5/src/dev/x86/ |
H A D | Pc.py | 32 from m5.objects.Device import IsaFake 33 from m5.objects.Platform import Platform 34 from m5.objects.SouthBridge import SouthBridge 35 from m5.objects.Terminal import Terminal 36 from m5.objects.Uart import Uart8250 37 from m5.objects.PciHost import GenericPciHost
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/gem5/configs/boot/ |
H A D | art.rcS | 3 #/benchmarks/spec/art00/art -scanfile c756hel.in -trainfile1 a10.img -stride 2 -startx 134 -starty 220 -endx 184 -endy 240 -objects 3 6 /benchmarks/spec/art00/art -scanfile c756hel.in -trainfile1 a10.img -stride 5 -startx 134 -starty 220 -endx 184 -endy 240 -objects 1
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/gem5/src/cpu/kvm/ |
H A D | BaseKvmCPU.py | 42 from m5.objects.BaseCPU import BaseCPU 43 from m5.objects.KvmVM import KvmVM
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/gem5/src/cpu/simple/ |
H A D | AtomicSimpleCPU.py | 42 from m5.objects.BaseSimpleCPU import BaseSimpleCPU 43 from m5.objects.SimPoint import SimPoint
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/gem5/src/dev/arm/ |
H A D | UFSHostDevice.py | 41 from m5.objects.Device import DmaDevice 42 from m5.objects.AbstractNVM import * 60 # the number of flash objects that are created. Each logic unit can have
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/gem5/src/dev/virtio/ |
H A D | VirtIO.py | 43 from m5.objects.Device import PioDevice 44 from m5.objects.PciDevice import PciDevice
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/gem5/src/dev/serial/ |
H A D | Uart.py | 44 from m5.objects.Device import BasicPioDevice 45 from m5.objects.Serial import SerialDevice
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/gem5/src/mem/qos/ |
H A D | QoSMemCtrl.py | 39 from m5.objects.AbstractMemory import AbstractMemory 40 from m5.objects.QoSTurnaround import *
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/gem5/src/mem/ruby/network/ |
H A D | Network.py | 31 from m5.objects.ClockedObject import ClockedObject 32 from m5.objects.BasicLink import BasicLink
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/gem5/tests/configs/ |
H A D | o3-timing.py | 41 from m5.objects import *
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H A D | o3-timing-mt.py | 41 from m5.objects import *
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/gem5/configs/learning_gem5/part2/ |
H A D | hello_goodbye.py | 45 from m5.objects import * 54 # instantiate all of the objects we've created above
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H A D | run_simple.py | 44 from m5.objects import * 52 # instantiate all of the objects we've created above
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/gem5/src/arch/alpha/ |
H A D | AlphaTLB.py | 32 from m5.objects.BaseTLB import BaseTLB
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/gem5/src/arch/riscv/ |
H A D | RiscvSystem.py | 35 from m5.objects.System import System
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/gem5/src/base/vnc/ |
H A D | Vnc.py | 40 from m5.objects.Graphics import *
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