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13# Copyright (c) 2007 The Regents of The University of Michigan
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38#
39# Authors: Nathan Binkert
40
41from m5.params import *
42from m5.objects.BaseSimpleCPU import BaseSimpleCPU
43from m5.objects.SimPoint import SimPoint
44
45class AtomicSimpleCPU(BaseSimpleCPU):
46    """Simple CPU model executing a configurable number of
47    instructions per cycle. This model uses the simplified 'atomic'
48    memory mode."""
49
50    type = 'AtomicSimpleCPU'
51    cxx_header = "cpu/simple/atomic.hh"
52
53    @classmethod
54    def memory_mode(cls):
55        return 'atomic'
56
57    @classmethod
58    def support_take_over(cls):
59        return True
60
61    width = Param.Int(1, "CPU width")
62    simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
63    simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
64
65    def addSimPointProbe(self, interval):
66        simpoint = SimPoint()
67        simpoint.interval = interval
68        self.probeListener = simpoint
69