111156Sandreas.sandberg@arm.com# Copyright (c) 2013, 2015 ARM Limited
29792SN/A# All rights reserved.
39792SN/A#
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59792SN/A# not be construed as granting a license to any other intellectual
69792SN/A# property including but not limited to intellectual property relating
79792SN/A# to a hardware implementation of the functionality of the software
89792SN/A# licensed hereunder.  You may use the software subject to the license
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109792SN/A# unmodified and in its entirety in all distributions of the software,
119792SN/A# modified or unmodified, in source code or in binary form.
129792SN/A#
134030SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
143096SN/A# All rights reserved.
153096SN/A#
163096SN/A# Redistribution and use in source and binary forms, with or without
173096SN/A# modification, are permitted provided that the following conditions are
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203096SN/A# redistributions in binary form must reproduce the above copyright
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253096SN/A# this software without specific prior written permission.
263096SN/A#
273096SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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383096SN/A#
399792SN/A# Authors: Andreas Hansson
403096SN/A
413096SN/Afrom m5.objects import *
4210406SN/Afrom m5.defines import buildEnv
439792SN/Afrom base_config import *
4410406SN/Afrom arm_generic import *
4512097Sandreas.sandberg@arm.comfrom common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
468134SN/A
4710406SN/A# If we are running ARM regressions, use a more sensible CPU
4810406SN/A# configuration. This makes the results more meaningful, and also
4910406SN/A# increases the coverage of the regressions.
5010406SN/Aif buildEnv['TARGET_ISA'] == "arm":
5111837Swendy.elsasser@arm.com    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
5211156Sandreas.sandberg@arm.com                                   cpu_class=O3_ARM_v7a_3,
5311156Sandreas.sandberg@arm.com                                   num_threads=2).create_root()
5410406SN/Aelse:
5511837Swendy.elsasser@arm.com    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
5611156Sandreas.sandberg@arm.com                                    cpu_class=DerivO3CPU,
5711156Sandreas.sandberg@arm.com                                    num_threads=2).create_root()
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