1# Copyright (c) 2013, 2015 ARM Limited
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3#
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan
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23# neither the name of the copyright holders nor the names of its
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25# this software without specific prior written permission.
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27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38#
39# Authors: Andreas Hansson
40
41from m5.objects import *
42from m5.defines import buildEnv
43from base_config import *
44from arm_generic import *
45from common.cores.arm.O3_ARM_v7a import O3_ARM_v7a_3
46
47# If we are running ARM regressions, use a more sensible CPU
48# configuration. This makes the results more meaningful, and also
49# increases the coverage of the regressions.
50if buildEnv['TARGET_ISA'] == "arm":
51    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
52                                   cpu_class=O3_ARM_v7a_3,
53                                   num_threads=2).create_root()
54else:
55    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_8x8,
56                                    cpu_class=DerivO3CPU,
57                                    num_threads=2).create_root()
58