112941Sandreas.sandberg@arm.com# Copyright (c) 2012, 2017-2018 ARM Limited
29520SAndreas.Sandberg@ARM.com# All rights reserved.
39520SAndreas.Sandberg@ARM.com#
49520SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall
59520SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual
69520SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating
79520SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software
89520SAndreas.Sandberg@ARM.com# licensed hereunder.  You may use the software subject to the license
99520SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated
109520SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software,
119520SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form.
129520SAndreas.Sandberg@ARM.com#
139520SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without
149520SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are
159520SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright
169520SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer;
179520SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright
189520SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the
199520SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution;
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219520SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from
229520SAndreas.Sandberg@ARM.com# this software without specific prior written permission.
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249520SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
259520SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
269520SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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359520SAndreas.Sandberg@ARM.com#
369520SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg
379520SAndreas.Sandberg@ARM.com
3812564Sgabeblack@google.comfrom __future__ import print_function
3913774Sandreas.sandberg@arm.comfrom __future__ import absolute_import
4012564Sgabeblack@google.com
4112095Sandreas.sandberg@arm.comfrom m5 import fatal
429520SAndreas.Sandberg@ARM.comimport m5.objects
439520SAndreas.Sandberg@ARM.comimport inspect
449520SAndreas.Sandberg@ARM.comimport sys
4511995Sgabeblack@google.comfrom textwrap import TextWrapper
469520SAndreas.Sandberg@ARM.com
479520SAndreas.Sandberg@ARM.com# Dictionary of mapping names of real CPU models to classes.
489520SAndreas.Sandberg@ARM.com_cpu_classes = {}
499520SAndreas.Sandberg@ARM.com
509520SAndreas.Sandberg@ARM.com
519520SAndreas.Sandberg@ARM.comdef is_cpu_class(cls):
529520SAndreas.Sandberg@ARM.com    """Determine if a class is a CPU that can be instantiated"""
539520SAndreas.Sandberg@ARM.com
549520SAndreas.Sandberg@ARM.com    # We can't use the normal inspect.isclass because the ParamFactory
559520SAndreas.Sandberg@ARM.com    # and ProxyFactory classes have a tendency to confuse it.
569520SAndreas.Sandberg@ARM.com    try:
579520SAndreas.Sandberg@ARM.com        return issubclass(cls, m5.objects.BaseCPU) and \
589520SAndreas.Sandberg@ARM.com            not cls.abstract and \
599520SAndreas.Sandberg@ARM.com            not issubclass(cls, m5.objects.CheckerCPU)
6011688Sandreas.hansson@arm.com    except (TypeError, AttributeError):
619520SAndreas.Sandberg@ARM.com        return False
629520SAndreas.Sandberg@ARM.com
6312941Sandreas.sandberg@arm.comdef _cpu_subclass_tester(name):
6412941Sandreas.sandberg@arm.com    cpu_class = getattr(m5.objects, name, None)
6512941Sandreas.sandberg@arm.com
6612941Sandreas.sandberg@arm.com    def tester(cls):
6712941Sandreas.sandberg@arm.com        return cpu_class is not None and cls is not None and \
6812941Sandreas.sandberg@arm.com            issubclass(cls, cpu_class)
6912941Sandreas.sandberg@arm.com
7012941Sandreas.sandberg@arm.com    return tester
7112941Sandreas.sandberg@arm.com
7212941Sandreas.sandberg@arm.comis_kvm_cpu = _cpu_subclass_tester("BaseKvmCPU")
7313012Sandreas.sandberg@arm.comis_atomic_cpu = _cpu_subclass_tester("AtomicSimpleCPU")
7413684Sgiacomo.travaglini@arm.comis_noncaching_cpu = _cpu_subclass_tester("NonCachingSimpleCPU")
7512941Sandreas.sandberg@arm.com
769520SAndreas.Sandberg@ARM.comdef get(name):
779520SAndreas.Sandberg@ARM.com    """Get a CPU class from a user provided class name or alias."""
789520SAndreas.Sandberg@ARM.com
799520SAndreas.Sandberg@ARM.com    try:
8011995Sgabeblack@google.com        cpu_class = _cpu_classes[name]
819520SAndreas.Sandberg@ARM.com        return cpu_class
829520SAndreas.Sandberg@ARM.com    except KeyError:
8312564Sgabeblack@google.com        print("%s is not a valid CPU model." % (name,))
849520SAndreas.Sandberg@ARM.com        sys.exit(1)
859520SAndreas.Sandberg@ARM.com
869520SAndreas.Sandberg@ARM.comdef print_cpu_list():
879520SAndreas.Sandberg@ARM.com    """Print a list of available CPU classes including their aliases."""
889520SAndreas.Sandberg@ARM.com
8912564Sgabeblack@google.com    print("Available CPU classes:")
909520SAndreas.Sandberg@ARM.com    doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
919520SAndreas.Sandberg@ARM.com    for name, cls in _cpu_classes.items():
9212564Sgabeblack@google.com        print("\t%s" % name)
939520SAndreas.Sandberg@ARM.com
949520SAndreas.Sandberg@ARM.com        # Try to extract the class documentation from the class help
959520SAndreas.Sandberg@ARM.com        # string.
969520SAndreas.Sandberg@ARM.com        doc = inspect.getdoc(cls)
979520SAndreas.Sandberg@ARM.com        if doc:
989520SAndreas.Sandberg@ARM.com            for line in doc_wrapper.wrap(doc):
9912564Sgabeblack@google.com                print(line)
1009520SAndreas.Sandberg@ARM.com
1019520SAndreas.Sandberg@ARM.comdef cpu_names():
1029520SAndreas.Sandberg@ARM.com    """Return a list of valid CPU names."""
10313731Sandreas.sandberg@arm.com    return list(_cpu_classes.keys())
1049520SAndreas.Sandberg@ARM.com
10511251Sradhika.jagtap@ARM.comdef config_etrace(cpu_cls, cpu_list, options):
10611251Sradhika.jagtap@ARM.com    if issubclass(cpu_cls, m5.objects.DerivO3CPU):
10711251Sradhika.jagtap@ARM.com        # Assign the same file name to all cpus for now. This must be
10811251Sradhika.jagtap@ARM.com        # revisited when creating elastic traces for multi processor systems.
10911251Sradhika.jagtap@ARM.com        for cpu in cpu_list:
11011251Sradhika.jagtap@ARM.com            # Attach the elastic trace probe listener. Set the protobuf trace
11111251Sradhika.jagtap@ARM.com            # file names. Set the dependency window size equal to the cpu it
11211251Sradhika.jagtap@ARM.com            # is attached to.
11311251Sradhika.jagtap@ARM.com            cpu.traceListener = m5.objects.ElasticTrace(
11411251Sradhika.jagtap@ARM.com                                instFetchTraceFile = options.inst_trace_file,
11511251Sradhika.jagtap@ARM.com                                dataDepTraceFile = options.data_trace_file,
11611251Sradhika.jagtap@ARM.com                                depWindowSize = 3 * cpu.numROBEntries)
11711251Sradhika.jagtap@ARM.com            # Make the number of entries in the ROB, LQ and SQ very
11811251Sradhika.jagtap@ARM.com            # large so that there are no stalls due to resource
11911251Sradhika.jagtap@ARM.com            # limitation as such stalls will get captured in the trace
12011251Sradhika.jagtap@ARM.com            # as compute delay. For replay, ROB, LQ and SQ sizes are
12111251Sradhika.jagtap@ARM.com            # modelled in the Trace CPU.
12211251Sradhika.jagtap@ARM.com            cpu.numROBEntries = 512;
12311251Sradhika.jagtap@ARM.com            cpu.LQEntries = 128;
12411251Sradhika.jagtap@ARM.com            cpu.SQEntries = 128;
12511251Sradhika.jagtap@ARM.com    else:
12611251Sradhika.jagtap@ARM.com        fatal("%s does not support data dependency tracing. Use a CPU model of"
12711251Sradhika.jagtap@ARM.com              " type or inherited from DerivO3CPU.", cpu_cls)
12811251Sradhika.jagtap@ARM.com
1299520SAndreas.Sandberg@ARM.com# Add all CPUs in the object hierarchy.
1309520SAndreas.Sandberg@ARM.comfor name, cls in inspect.getmembers(m5.objects, is_cpu_class):
1319520SAndreas.Sandberg@ARM.com    _cpu_classes[name] = cls
13212098Sandreas.sandberg@arm.com
13312152Sandreas.sandberg@arm.com
13412152Sandreas.sandberg@arm.comfrom m5.defines import buildEnv
13512152Sandreas.sandberg@arm.comfrom importlib import import_module
13612152Sandreas.sandberg@arm.comfor package in [ "generic", buildEnv['TARGET_ISA']]:
13712152Sandreas.sandberg@arm.com    try:
13813774Sandreas.sandberg@arm.com        package = import_module(".cores." + package,
13913774Sandreas.sandberg@arm.com                                package=__name__.rpartition('.')[0])
14012152Sandreas.sandberg@arm.com    except ImportError:
14112152Sandreas.sandberg@arm.com        # No timing models for this ISA
14212152Sandreas.sandberg@arm.com        continue
14312152Sandreas.sandberg@arm.com
14412152Sandreas.sandberg@arm.com    for mod_name, module in inspect.getmembers(package, inspect.ismodule):
14512152Sandreas.sandberg@arm.com        for name, cls in inspect.getmembers(module, is_cpu_class):
14612152Sandreas.sandberg@arm.com            _cpu_classes[name] = cls
147