src/cpu/BaseCPU.py

55 from m5.objects.ClockedObject import ClockedObject
56 from m5.objects.XBar import L2XBar
57 from m5.objects.InstTracer import InstTracer
58 from m5.objects.CPUTracers import ExeTracer
59 from m5.objects.SubSystem import SubSystem
60 from m5.objects.ClockDomain import *
61 from m5.objects.Platform import Platform
66     from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
67     from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts
68     from m5.objects.AlphaISA import AlphaISA as ArchISA
72     from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
73     from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
74     from m5.objects.SparcISA import SparcISA as ArchISA
78     from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
79     from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
80     from m5.objects.X86ISA import X86ISA as ArchISA
84     from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
85     from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
86     from m5.objects.MipsISA import MipsISA as ArchISA
90     from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
91     from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
92     from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
93     from m5.objects.ArmISA import ArmISA as ArchISA
97     from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
98     from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
99     from m5.objects.PowerISA import PowerISA as ArchISA
103     from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
104     from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
105     from m5.objects.RiscvISA import RiscvISA as ArchISA