19651SAndreas.Sandberg@ARM.com# Copyright (c) 2012 ARM Limited
29651SAndreas.Sandberg@ARM.com# All rights reserved.
39651SAndreas.Sandberg@ARM.com#
49651SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall
59651SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual
69651SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating
79651SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software
89651SAndreas.Sandberg@ARM.com# licensed hereunder.  You may use the software subject to the license
99651SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated
109651SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software,
119651SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form.
129651SAndreas.Sandberg@ARM.com#
139651SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without
149651SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are
159651SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright
169651SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer;
179651SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright
189651SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the
199651SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution;
209651SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its
219651SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from
229651SAndreas.Sandberg@ARM.com# this software without specific prior written permission.
239651SAndreas.Sandberg@ARM.com#
249651SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
259651SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
269651SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
279651SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
289651SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
299651SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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319651SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
329651SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
339651SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
349651SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
359651SAndreas.Sandberg@ARM.com#
369651SAndreas.Sandberg@ARM.com# Authors: Andreas Sandberg
379651SAndreas.Sandberg@ARM.com
3811988Sandreas.sandberg@arm.comfrom m5.SimObject import *
399651SAndreas.Sandberg@ARM.comfrom m5.params import *
409651SAndreas.Sandberg@ARM.comfrom m5.proxy import *
419651SAndreas.Sandberg@ARM.com
4213665Sandreas.sandberg@arm.comfrom m5.objects.BaseCPU import BaseCPU
4313665Sandreas.sandberg@arm.comfrom m5.objects.KvmVM import KvmVM
449651SAndreas.Sandberg@ARM.com
459651SAndreas.Sandberg@ARM.comclass BaseKvmCPU(BaseCPU):
469651SAndreas.Sandberg@ARM.com    type = 'BaseKvmCPU'
479651SAndreas.Sandberg@ARM.com    cxx_header = "cpu/kvm/base.hh"
489651SAndreas.Sandberg@ARM.com    abstract = True
499651SAndreas.Sandberg@ARM.com
5011988Sandreas.sandberg@arm.com    @cxxMethod
5111988Sandreas.sandberg@arm.com    def dump(self):
5211988Sandreas.sandberg@arm.com        """Dump the internal state of KVM to standard out."""
5311988Sandreas.sandberg@arm.com        pass
549651SAndreas.Sandberg@ARM.com
559651SAndreas.Sandberg@ARM.com    @classmethod
569651SAndreas.Sandberg@ARM.com    def memory_mode(cls):
579651SAndreas.Sandberg@ARM.com        return 'atomic_noncaching'
589651SAndreas.Sandberg@ARM.com
599651SAndreas.Sandberg@ARM.com    @classmethod
609651SAndreas.Sandberg@ARM.com    def require_caches(cls):
619651SAndreas.Sandberg@ARM.com        return False
629651SAndreas.Sandberg@ARM.com
639651SAndreas.Sandberg@ARM.com    @classmethod
649651SAndreas.Sandberg@ARM.com    def support_take_over(cls):
659651SAndreas.Sandberg@ARM.com        return True
669651SAndreas.Sandberg@ARM.com
679690Sandreas@sandberg.pp.se    useCoalescedMMIO = Param.Bool(False, "Use coalesced MMIO (EXPERIMENTAL)")
689655SAndreas.Sandberg@ARM.com    usePerfOverflow = Param.Bool(False, "Use perf event overflow counters (EXPERIMENTAL)")
6911399Sandreas.sandberg@arm.com    alwaysSyncTC = Param.Bool(False,
7011399Sandreas.sandberg@arm.com                              "Always sync thread contexts on entry/exit")
719754Sandreas@sandberg.pp.se
729754Sandreas@sandberg.pp.se    hostFreq = Param.Clock("2GHz", "Host clock frequency")
739651SAndreas.Sandberg@ARM.com    hostFactor = Param.Float(1.0, "Cycle scale factor")
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