16876Ssteve.reinhardt@amd.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
26876Ssteve.reinhardt@amd.com# All rights reserved.
36876Ssteve.reinhardt@amd.com#
46876Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without
56876Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are
66876Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright
76876Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer;
86876Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright
96876Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the
106876Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution;
116876Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its
126876Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from
136876Ssteve.reinhardt@amd.com# this software without specific prior written permission.
146876Ssteve.reinhardt@amd.com#
156876Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
166876Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
176876Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
186876Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
196876Ssteve.reinhardt@amd.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
206876Ssteve.reinhardt@amd.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
216876Ssteve.reinhardt@amd.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
226876Ssteve.reinhardt@amd.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
236876Ssteve.reinhardt@amd.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
246876Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
256876Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
266876Ssteve.reinhardt@amd.com#
276876Ssteve.reinhardt@amd.com# Authors: Steve Reinhardt
286876Ssteve.reinhardt@amd.com#          Brad Beckmann
296876Ssteve.reinhardt@amd.com
306876Ssteve.reinhardt@amd.comfrom m5.params import *
3113665Sandreas.sandberg@arm.comfrom m5.objects.ClockedObject import ClockedObject
3213665Sandreas.sandberg@arm.comfrom m5.objects.BasicLink import BasicLink
336879Ssteve.reinhardt@amd.com
349465Snilay@cs.wisc.educlass RubyNetwork(ClockedObject):
356876Ssteve.reinhardt@amd.com    type = 'RubyNetwork'
366876Ssteve.reinhardt@amd.com    cxx_class = 'Network'
379338SAndreas.Sandberg@arm.com    cxx_header = "mem/ruby/network/Network.hh"
386876Ssteve.reinhardt@amd.com    abstract = True
399594Snilay@cs.wisc.edu    topology = Param.String("Not Specified",
409594Snilay@cs.wisc.edu                            "the name of the imported topology module")
419594Snilay@cs.wisc.edu
4211065Snilay@cs.wisc.edu    number_of_virtual_networks = Param.Unsigned("Number of virtual networks "
4311065Snilay@cs.wisc.edu           "used by the coherence protocol in use.  The on-chip network "
4411065Snilay@cs.wisc.edu           "assumes the protocol numbers vnets starting from 0.  Therefore, "
4511065Snilay@cs.wisc.edu           "the number of virtual networks should be one more than the "
4611065Snilay@cs.wisc.edu           "highest numbered vnet in use.")
479594Snilay@cs.wisc.edu    control_msg_size = Param.Int(8, "")
489594Snilay@cs.wisc.edu    ruby_system = Param.RubySystem("")
499594Snilay@cs.wisc.edu
509593Snilay@cs.wisc.edu    routers = VectorParam.BasicRouter("Network routers")
5110122Snilay@cs.wisc.edu    netifs = VectorParam.ClockedObject("Network Interfaces")
529594Snilay@cs.wisc.edu    ext_links = VectorParam.BasicExtLink("Links to external nodes")
539594Snilay@cs.wisc.edu    int_links = VectorParam.BasicIntLink("Links between internal nodes")
5410311Snilay@cs.wisc.edu
5510311Snilay@cs.wisc.edu    slave = VectorSlavePort("CPU slave port")
5610311Snilay@cs.wisc.edu    master = VectorMasterPort("CPU master port")
57