1# -*- mode:python -*-
2
3# Copyright (c) 2014, 2016 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder.  You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Redistribution and use in source and binary forms, with or without
16# modification, are permitted provided that the following conditions are
17# met: redistributions of source code must retain the above copyright
18# notice, this list of conditions and the following disclaimer;
19# redistributions in binary form must reproduce the above copyright
20# notice, this list of conditions and the following disclaimer in the
21# documentation and/or other materials provided with the distribution;
22# neither the name of the copyright holders nor the names of its
23# contributors may be used to endorse or promote products derived from
24# this software without specific prior written permission.
25#
26# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
29# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
30# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
31# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
32# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
33# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37#
38# Authors: Andreas Sandberg
39
40from m5.SimObject import SimObject
41from m5.params import *
42from m5.proxy import *
43from m5.objects.Device import PioDevice
44from m5.objects.PciDevice import PciDevice
45
46
47class VirtIODeviceBase(SimObject):
48    type = 'VirtIODeviceBase'
49    cxx_header = 'dev/virtio/base.hh'
50    abstract = True
51
52    subsystem = Param.UInt8(0x00, "VirtIO subsystem ID")
53
54    system = Param.System(Parent.any, "system object")
55
56class VirtIODummyDevice(VirtIODeviceBase):
57    type = 'VirtIODummyDevice'
58    cxx_header = 'dev/virtio/base.hh'
59
60class PciVirtIO(PciDevice):
61    type = 'PciVirtIO'
62    cxx_header = 'dev/virtio/pci.hh'
63
64    vio = Param.VirtIODeviceBase(VirtIODummyDevice(), "VirtIO device")
65
66    VendorID = 0x1AF4
67    SubsystemVendorID = VendorID;
68    DeviceID = 0x1000
69
70    ClassCode = 0xff # Misc device
71
72    BAR0 = 0x00000001 # Anywhere in 32-bit space; IOREG
73    BAR0Size = '0B' # Overridden by the device model
74
75    InterruptPin = 0x01 # Use #INTA
76