1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31
32from m5.objects.Device import IsaFake
33from m5.objects.Platform import Platform
34from m5.objects.SouthBridge import SouthBridge
35from m5.objects.Terminal import Terminal
36from m5.objects.Uart import Uart8250
37from m5.objects.PciHost import GenericPciHost
38
39def x86IOAddress(port):
40    IO_address_space_base = 0x8000000000000000
41    return IO_address_space_base + port;
42
43class PcPciHost(GenericPciHost):
44    conf_base = 0xC000000000000000
45    conf_size = "16MB"
46
47    pci_pio_base = 0x8000000000000000
48
49class Pc(Platform):
50    type = 'Pc'
51    cxx_header = "dev/x86/pc.hh"
52    system = Param.System(Parent.any, "system")
53
54    south_bridge = SouthBridge()
55    pci_host = PcPciHost()
56
57    # "Non-existant" ports used for timing purposes by the linux kernel
58    i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
59    i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1)
60
61    # Ports behind the pci config and data regsiters. These don't do anything,
62    # but the linux kernel fiddles with them anway.
63    behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
64
65    # Serial port and terminal
66    com_1 = Uart8250()
67    com_1.pio_addr = x86IOAddress(0x3f8)
68    com_1.device = Terminal()
69
70    # Devices to catch access to non-existant serial ports.
71    fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8)
72    fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8)
73    fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8)
74
75    # A device to catch accesses to the non-existant floppy controller.
76    fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2)
77
78    def attachIO(self, bus, dma_ports = []):
79        self.south_bridge.attachIO(bus, dma_ports)
80        self.i_dont_exist1.pio = bus.master
81        self.i_dont_exist2.pio = bus.master
82        self.behind_pci.pio = bus.master
83        self.com_1.pio = bus.master
84        self.fake_com_2.pio = bus.master
85        self.fake_com_3.pio = bus.master
86        self.fake_com_4.pio = bus.master
87        self.fake_floppy.pio = bus.master
88        self.pci_host.pio = bus.default
89