Searched refs:cpu (Results 51 - 75 of 194) sorted by relevance

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/gem5/src/cpu/o3/
H A Dthread_state.hh48 #include "cpu/thread_context.hh"
49 #include "cpu/thread_state.hh"
74 O3CPU *cpu; member in struct:O3ThreadState
93 cpu(_cpu), noSquashFromTC(false), trapPending(false),
99 if (cpu->params()->profile) {
101 cpu->params()->system->kernelSymtab);
151 simout.create(csprintf("profile.%s.dat", cpu->name())));
H A Dthread_context.hh48 #include "cpu/o3/isa_specific.hh"
49 #include "cpu/thread_context.hh"
76 O3CPU *cpu; member in class:O3ThreadContext
82 BaseTLB *getITBPtr() override { return cpu->itb; }
85 BaseTLB *getDTBPtr() override { return cpu->dtb; }
92 return cpu->isa[thread->threadId()];
98 return cpu->fetch.decoder[thread->threadId()];
102 BaseCPU *getCpuPtr() override { return cpu; }
105 int cpuId() const override { return cpu->cpuId(); }
108 uint32_t socketId() const override { return cpu
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/gem5/util/cpt_upgraders/
H A Darm-gicv2-banked-regs.py36 # duplicate banked registers into new per-cpu arrays.
71 for cpu in xrange(0, 255):
72 if cpuEnabled[cpu] == 'true':
73 intPriority = b_intPriority[cpu*32 : (cpu+1)*32]
74 new_sec = "%s.bankedRegs%u" % (sec, cpu)
/gem5/src/dev/arm/
H A Dgic_v2.cc89 // Initialize cpu highest int
299 DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr,
366 "CPU %d reading IAR.id=%d IAR.cpu=%d, iar=0x%x\n",
383 panic("Tried to read Gic cpu at offset %#x\n", daddr);
566 DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n",
618 DPRINTF(Interrupt, "CPU %d done handling intr IAR = %d from cpu %d\n",
632 panic("Tried to write Gic cpu at offset %#x\n", daddr);
676 // Interrupt requesting cpu onl
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H A Dvgic.cc126 DPRINTF(VGIC, "Consumed interrupt %d (cpu%d) from LR%d (EOI%d)\n",
265 DPRINTF(VGIC, "EOIR: No LR for irq %d(cpu%d)\n", virq, vcpu);
267 DPRINTF(VGIC, "EOIR: Found LR%d for irq %d(cpu%d)\n", i, virq, vcpu);
364 VGic::postVInt(uint32_t cpu, Tick when)
366 DPRINTF(VGIC, "Posting VIRQ to %d\n", cpu);
367 if (!(postVIntEvent[cpu]->scheduled()))
368 eventq->schedule(postVIntEvent[cpu], when);
372 VGic::unPostVInt(uint32_t cpu)
374 DPRINTF(VGIC, "Unposting VIRQ to %d\n", cpu);
375 platform->intrctrl->clear(cpu, ArmIS
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H A Dgic_v3.hh105 void clearPPInt(uint32_t int_id, uint32_t cpu) override;
124 void sendPPInt(uint32_t int_id, uint32_t cpu) override;
132 void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
161 void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
/gem5/tests/gem5/cpu_tests/
H A Dtest.py59 for cpu in valid_isas[isa]:
61 name='cpu_test_{}_{}'.format(cpu,workload),
64 config_args=['--cpu={}'.format(cpu), binary],
/gem5/configs/common/
H A DCpuConfig.py109 for cpu in cpu_list:
111 # file names. Set the dependency window size equal to the cpu it
113 cpu.traceListener = m5.objects.ElasticTrace(
116 depWindowSize = 3 * cpu.numROBEntries)
122 cpu.numROBEntries = 512;
123 cpu.LQEntries = 128;
124 cpu.SQEntries = 128;
/gem5/tests/long/se/70.twolf/
H A Dtest.py36 root.system.cpu[0].workload = workload.makeProcess()
37 cwd = root.system.cpu[0].workload[0].cwd
/gem5/tests/quick/se/70.twolf/
H A Dtest.py37 root.system.cpu[0].workload = workload.makeProcess()
38 cwd = root.system.cpu[0].workload[0].cwd
/gem5/tests/configs/
H A Dtwosys-tsunami-simple-atomic.py45 test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
47 test_sys.cpu.createInterruptController()
48 test_sys.cpu.connectAllPorts(test_sys.membus)
52 test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
80 drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
82 drive_sys.cpu.createInterruptController()
83 drive_sys.cpu.connectAllPorts(drive_sys.membus)
87 drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz',
H A Dbase_config.py96 def create_caches_private(self, cpu):
100 cpu -- CPU instance to work on.
102 cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
121 def init_cpu(self, system, cpu, sha_bus):
126 cpu -- CPU to initialize.
128 if not cpu.switched_out:
129 self.create_caches_private(cpu)
130 cpu.createInterruptController()
131 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
149 system.cpu
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H A Dx86_generic.py84 def create_caches_private(self, cpu):
85 cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
103 def create_caches_private(self, cpu):
104 cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1),
/gem5/util/stats/
H A Dprofile.py244 self.cpu = 0
265 def setdata(self, run, cpu, data):
269 if cpu in self.data[run]:
271 'data already stored for run %s and cpu %s' % (run, cpu)
273 self.data[run][cpu] = data
275 def getdata(self, run, cpu):
277 return self.data[run][cpu]
279 print run, cpu
284 for cpu,dat
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/gem5/configs/example/arm/
H A Dfs_power.py106 for cpu in root.system.descendants():
107 if not isinstance(cpu, m5.objects.BaseCPU):
110 cpu.default_p_state = "ON"
111 cpu.power_model = CpuPowerModel()
/gem5/src/dev/
H A DPlatform.py40 def annotateCpuDeviceNode(self, cpu, state):
/gem5/tests/gem5/memory/
H A Dsimple-run.py50 # even if this is only a traffic generator, call it cpu to make sure
53 cpu = TrafficGen( variable
68 system = System(cpu = cpu, physmem = MyMem(),
81 system.cpu.port = system.monitor.slave
/gem5/configs/learning_gem5/part1/
H A Dcaches.py69 def connectCPU(self, cpu):
89 def connectCPU(self, cpu):
91 self.cpu_side = cpu.icache_port
108 def connectCPU(self, cpu):
110 self.cpu_side = cpu.dcache_port
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py78 [L1Cache(system, self, cpu) for cpu in cpus] + \
108 # Connect the cpu's cache, interrupt, and TLB ports to Ruby
109 for i,cpu in enumerate(cpus):
110 cpu.icache_port = self.sequencers[i].slave
111 cpu.dcache_port = self.sequencers[i].slave
114 cpu.interrupts[0].pio = self.sequencers[i].master
115 cpu.interrupts[0].int_master = self.sequencers[i].slave
116 cpu.interrupts[0].int_slave = self.sequencers[i].master
118 cpu
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H A Druby_caches_MI_example.py78 [L1Cache(system, self, cpu) for cpu in cpus] + \
106 # Connect the cpu's cache, interrupt, and TLB ports to Ruby
107 for i,cpu in enumerate(cpus):
108 cpu.icache_port = self.sequencers[i].slave
109 cpu.dcache_port = self.sequencers[i].slave
112 cpu.interrupts[0].pio = self.sequencers[i].master
113 cpu.interrupts[0].int_master = self.sequencers[i].slave
114 cpu.interrupts[0].int_slave = self.sequencers[i].master
116 cpu
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/gem5/src/cpu/minor/
H A Dexecute.cc40 #include "cpu/minor/execute.hh"
45 #include "cpu/minor/cpu.hh"
46 #include "cpu/minor/exec_context.hh"
47 #include "cpu/minor/fetch1.hh"
48 #include "cpu/minor/lsq.hh"
49 #include "cpu/op_class.hh"
70 cpu(cpu_),
143 FUPipeline *fu = new FUPipeline(fu_name.str(), *fu_description, cpu);
218 ThreadContext *thread = cpu
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H A Ddecode.cc40 #include "cpu/minor/decode.hh"
42 #include "cpu/minor/pipeline.hh"
55 cpu(cpu_),
110 MinorCPU &cpu)
112 inst->traceData = cpu.getTracer()->getInstRecord(curTick(),
113 cpu.getContext(inst->id.threadId),
134 for (ThreadID tid = 0; tid < cpu.numThreads; tid++)
235 dynInstAddTracing(output_inst, parent_static_inst, cpu);
276 cpu.activityRecorder->activity();
283 for (ThreadID i = 0; i < cpu
109 dynInstAddTracing(MinorDynInstPtr inst, StaticInstPtr static_inst, MinorCPU &cpu) argument
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/gem5/configs/example/
H A Dfs.py144 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
163 for (i, cpu) in enumerate(test_sys.cpu):
165 # Tie the cpu ports to the correct ruby system ports
167 cpu.clk_domain = test_sys.cpu_clk_domain
168 cpu.createThreads()
169 cpu.createInterruptController()
171 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
172 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
175 cpu
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H A Dapu_se.py79 parser.add_option("--cpu-only-mode", action="store_true", default=False,
126 parser.add_option("--cpu-voltage", action="store", type="string",
316 cpu = CpuClass(cpu_id = i, variable
321 cpu_list.append(cpu)
324 cpu.max_insts_any_thread = int(options.fast_forward)
342 cpu = MainCpuClass(cpu_id = i, variable
348 cpu.switched_out = True
349 future_cpu_list.append(cpu)
351 cpu_list.append(cpu)
395 for cpu i
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/gem5/util/tlm/conf/
H A Dtlm_slave.py59 system.cpu = TrafficGen(config_file = "conf/tgen.cfg")
70 system.cpu.port = system.membus.slave

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