dev-arm: Implement GIC-400 model from GicV2

Implementation registers for the GICv2 model currently hold values
referring to a GIC-400 implementation. This patch is making them
parametrizable so that it is possible to instantiate a GIC-400 model.
The patch is also modifying Realview platform to use new GIC-400 model
in lieau of GICv2.

Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15277
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Added unimplemented GICv2 GICC_DIR

This GICC CPU register is not implemented but just gives a warning.

Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15275
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Don't panic when EOIR a non active PPI

GIC architecture specification says that writing EOIR with
a not active irq it is an unpredictable behavior.
So, just warn when it happens for a PPI case, like it is
already done in SPI case.

Change-Id: Icb1b8f5690d5e87b15c3b0fe2ca0d37fdd4085ee
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13556
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arm: Use little endian packet accessors.

We know data is little endian, so we can use those accessors
explicitly.

Change-Id: Iee337109fcda134e1ac5a700e5141fd7060f9c45
Reviewed-on: https://gem5-review.googlesource.com/c/13457
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Enable FIQ signaling for Group0 interrupts in GICv2

Change-Id: Iafaf26344a26eade60c08dd2c0d716af14d9b328
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12948
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Create postFiq events for GICv2

GICv2 is signaling IRQs only to the CPU. This patch is adding the
capability of scheduling FIQs.

Change-Id: I395afc83eb8d58cfd32cd93372bcb6f804364ef5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12947
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Implement GICv2 GICD_IGROUPR register

This patch is implementing GICD_IGROUPR register.

Change-Id: I1626f61fbf7deec9c81d8d2c135f1d6c0c4eb891
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12946
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Fix GICv2 cpu interrupt enable flag

Read/WriteCpu methods in the GICv2 are accessing the GICC_CTRL register
as if writing any non-zero value to the register will enable IRQ
signaling to the CPU. Instead, only the 2 least significant bits
control group0/group1 enablement. This patch is renaming GICC_CTRL
underlying data buffer from cpuEnabled to cpuControl and it is making it
an array of uint32_t instead of bool. cpuEnabled now becomes a method
and checks if GICC_CTRL.EnableGrp0 or GICC_CTRL.EnableGrp0 are set.

Change-Id: I40f0b3c52c40abd482a856f032bf3686f96ef641
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12945
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Add basic support for level sensitive SPIs in GICv2

For level sensitive interrupt IRQ line must be cleared when interrupt is
deasserted. This is not the case for edge-trigerred interrupt.

Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130
Reviewed-on: https://gem5-review.googlesource.com/12944
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Take into account PPI enable bit

When checking for PPIs to send to the cpu in the PL390 GIC we
were forwarding any pending PPI regardless of their masking
in the distributor.

Change-Id: I2e294abeca733cca95cd0deeb9659c7d3d9d8734
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12624
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: rename Pl390 to GicV2

The Pl390 model has evolved and acquired a lot of the features from GICv2,
which means that the name is no longer appropriate. Rename it to GICv2
since this is more representative of the supported features.

GICv2 is backwards compatible with the older Pl390, so we decided to
simply rename the class to represent both GICv2 and older interfaces such
as the instead of creating a new separate one.

Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12492
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>