Lines Matching refs:cpu
96 def create_caches_private(self, cpu):
100 cpu -- CPU instance to work on.
102 cpu.addPrivateSplitL1Caches(L1_ICache(size='32kB', assoc=1),
121 def init_cpu(self, system, cpu, sha_bus):
126 cpu -- CPU to initialize.
128 if not cpu.switched_out:
129 self.create_caches_private(cpu)
130 cpu.createInterruptController()
131 cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
149 system.cpu = self.create_cpus(system.cpu_clk_domain)
152 any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
181 for i, cpu in enumerate(system.cpu):
182 if not cpu.switched_out:
183 cpu.createInterruptController()
184 cpu.connectCachedPorts(system.ruby._cpu_ports[i])
187 for cpu in system.cpu:
188 self.init_cpu(system, cpu, sha_bus)
252 def create_caches_private(self, cpu):
256 cpu.addTwoLevelCacheHierarchy(L1_ICache(size='128kB'),
315 def create_caches_private(self, cpu):
316 cpu.addTwoLevelCacheHierarchy(L1_ICache(size='32kB', assoc=1),