Lines Matching refs:cpu
78 [L1Cache(system, self, cpu) for cpu in cpus] + \
106 # Connect the cpu's cache, interrupt, and TLB ports to Ruby
107 for i,cpu in enumerate(cpus):
108 cpu.icache_port = self.sequencers[i].slave
109 cpu.dcache_port = self.sequencers[i].slave
112 cpu.interrupts[0].pio = self.sequencers[i].master
113 cpu.interrupts[0].int_master = self.sequencers[i].slave
114 cpu.interrupts[0].int_slave = self.sequencers[i].master
116 cpu.itb.walker.port = self.sequencers[i].slave
117 cpu.dtb.walker.port = self.sequencers[i].slave
127 def __init__(self, system, ruby_system, cpu):
138 self.clk_domain = cpu.clk_domain
139 self.send_evictions = self.sendEvicts(cpu)
149 def sendEvicts(self, cpu):
156 if type(cpu) is DerivO3CPU or \