1/*
2 * Copyright (c) 2019 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2018 Metempsy Technology Consulting
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Jairo Balart
41 */
42
43#ifndef __DEV_ARM_GICV3_H__
44#define __DEV_ARM_GICV3_H__
45
46#include "dev/arm/base_gic.hh"
47#include "params/Gicv3.hh"
48
49class Gicv3CPUInterface;
50class Gicv3Distributor;
51class Gicv3Redistributor;
52class Gicv3Its;
53
54class Gicv3 : public BaseGic
55{
56  protected:
57    friend class Gicv3CPUInterface;
58    friend class Gicv3Redistributor;
59
60    typedef Gicv3Params Params;
61    Gicv3Distributor * distributor;
62    std::vector<Gicv3Redistributor *> redistributors;
63    std::vector<Gicv3CPUInterface *> cpuInterfaces;
64    Gicv3Its * its;
65    AddrRange distRange;
66    AddrRange redistRange;
67    AddrRangeList addrRanges;
68    uint64_t redistSize;
69
70  public:
71
72    // Special interrupt IDs, as per SPEC 2.2.1 section
73    static const int INTID_SECURE = 1020;
74    static const int INTID_NONSECURE = 1021;
75    static const int INTID_SPURIOUS = 1023;
76
77    // Number of Software Generated Interrupts
78    static const int SGI_MAX = 16;
79    // Number of Private Peripheral Interrupts
80    static const int PPI_MAX = 16;
81
82    // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
83    typedef enum {
84        INT_INACTIVE,
85        INT_PENDING,
86        INT_ACTIVE,
87        INT_ACTIVE_PENDING,
88    } IntStatus;
89
90    // Interrupt groups, as per SPEC section 4.6
91    typedef enum {
92        G0S,
93        G1S,
94        G1NS,
95    } GroupId;
96
97    typedef enum {
98        INT_LEVEL_SENSITIVE,
99        INT_EDGE_TRIGGERED,
100    } IntTriggerType;
101
102  protected:
103
104    void clearInt(uint32_t int_id) override;
105    void clearPPInt(uint32_t int_id, uint32_t cpu) override;
106
107    inline AddrRangeList
108    getAddrRanges() const override
109    {
110        return addrRanges;
111    }
112
113    void init() override;
114
115    const Params *
116    params() const
117    {
118        return dynamic_cast<const Params *>(_params);
119    }
120
121    Tick read(PacketPtr pkt) override;
122    void reset();
123    void sendInt(uint32_t int_id) override;
124    void sendPPInt(uint32_t int_id, uint32_t cpu) override;
125    void serialize(CheckpointOut & cp) const override;
126    void unserialize(CheckpointIn & cp) override;
127    Tick write(PacketPtr pkt) override;
128
129  public:
130
131    Gicv3(const Params * p);
132    void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
133
134    inline Gicv3CPUInterface *
135    getCPUInterface(int cpu_id) const
136    {
137        assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
138        return cpuInterfaces[cpu_id];
139    }
140
141    inline Gicv3Distributor *
142    getDistributor() const
143    {
144        return distributor;
145    }
146
147    inline Gicv3Redistributor *
148    getRedistributor(ContextID context_id) const
149    {
150        assert(context_id < redistributors.size() and
151               redistributors[context_id]);
152        return redistributors[context_id];
153    }
154
155    Gicv3Redistributor *
156    getRedistributorByAffinity(uint32_t affinity) const;
157
158    Gicv3Redistributor *
159    getRedistributorByAddr(Addr address) const;
160
161    void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
162};
163
164#endif //__DEV_ARM_GICV3_H__
165