Searched refs:cpu (Results 26 - 50 of 194) sorted by relevance

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/gem5/src/cpu/
H A Dintr_control.cc32 #include "cpu/intr_control.hh"
38 #include "cpu/base.hh"
39 #include "cpu/thread_context.hh"
52 DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
54 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); local
55 cpu->postInterrupt(tcvec[cpu_id]->threadId(), int_num, index);
61 DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
63 BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr(); local
64 cpu->clearInterrupt(tcvec[cpu_id]->threadId(), int_num, index);
H A Dbase_dyn_inst_impl.hh54 #include "cpu/base_dyn_inst.hh"
55 #include "cpu/exetrace.hh"
65 InstSeqNum seq_num, ImplCPU *cpu)
66 : staticInst(_staticInst), cpu(cpu),
114 // Also make this a parameter, or perhaps get it from xc or cpu.
121 ++cpu->instcount;
123 if (cpu->instcount > 1500) {
125 cpu->dumpInsts();
128 assert(cpu
62 BaseDynInst(const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop, TheISA::PCState _pc, TheISA::PCState _predPC, InstSeqNum seq_num, ImplCPU *cpu) argument
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/gem5/tests/configs/
H A Dtgen-dram-ctrl.py46 # even if this is only a traffic generator, call it cpu to make sure
48 cpu = TrafficGen( variable
52 system = System(cpu = cpu, physmem = DDR3_1600_8x8(),
62 system.cpu.port = system.monitor.slave
H A Dpc-simple-timing-ruby.py66 system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
79 for (i, cpu) in enumerate(system.cpu):
81 cpu.createInterruptController()
82 # Tie the cpu ports to the correct ruby system ports
83 cpu.icache_port = system.ruby._cpu_ports[i].slave
84 cpu.dcache_port = system.ruby._cpu_ports[i].slave
85 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
86 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
88 cpu
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H A Dsimple-timing-ruby.py63 cpu = TimingSimpleCPU(cpu_id=0) variable
64 system = System(cpu = cpu)
73 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
86 cpu.createInterruptController()
89 # Tie the cpu cache ports to the ruby cpu ports and
92 cpu.connectAllPorts(system.ruby._cpu_ports[0])
H A Dsimple-timing-mp-ruby.py68 system = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
72 system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
81 for (i, cpu) in enumerate(system.cpu):
83 cpu.createInterruptController()
86 # Tie the cpu ports to the ruby cpu ports
88 cpu.connectAllPorts(system.ruby._cpu_ports[i])
/gem5/tests/long/se/40.perlbmk/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/long/se/10.mcf/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/long/se/20.parser/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/long/se/50.vortex/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/long/se/30.eon/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/long/se/60.bzip2/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/quick/se/10.mcf/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/quick/se/30.eon/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/quick/se/50.vortex/
H A Dtest.py33 root.system.cpu[0].workload = workload.makeProcess()
/gem5/tests/quick/se/40.m5threads-test-atomic/
H A Dtest.py5 root.system.cpu[i].workload = process
/gem5/tests/quick/se/01.hello-2T-smt/
H A Dtest.py33 root.system.cpu[0].workload = [process1, process2]
/gem5/src/cpu/o3/
H A Dthread_context_impl.hh52 #include "cpu/o3/thread_context.hh"
53 #include "cpu/quiesce_event.hh"
100 cpu->activateContext(thread->threadId());
113 if (cpu->isDraining()) {
122 cpu->suspendContext(thread->threadId());
142 cpu->addThreadToExitingList(thread->threadId());
188 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
203 cpu->isa[thread->threadId()]->clear();
210 return cpu->readArchIntReg(reg_idx, thread->threadId());
217 return cpu
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H A Ddyn_inst.hh51 #include "cpu/o3/cpu.hh"
52 #include "cpu/o3/isa_specific.hh"
53 #include "cpu/base_dyn_inst.hh"
54 #include "cpu/inst_seq.hh"
55 #include "cpu/reg_class.hh"
83 InstSeqNum seq_num, O3CPU *cpu);
106 using BaseDynInst<Impl>::cpu;
142 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
178 return this->cpu
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/gem5/tests/quick/se/04.gpu/
H A Dtest.py47 root.system.cpu[2].cl_driver = driver
48 root.system.cpu[0].workload = Process(cmd = 'gpu-hello',
/gem5/src/dev/alpha/
H A DAlphaBackdoor.py38 cpu = Param.BaseCPU(Parent.cpu[0], "Processor") variable in class:AlphaBackdoor
/gem5/util/tlm/
H A Drun_gem5_fs.sh41 --cpu-type=TimingSimpleCPU \
42 --num-cpu=1 \
48 --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
/gem5/configs/example/
H A Dhmc_hello.py60 system.cpu = TimingSimpleCPU()
64 system.cpu.icache_port = system.membus.slave
65 system.cpu.dcache_port = system.membus.slave
67 system.cpu.createInterruptController()
79 # set the cpu workload
80 system.cpu.workload = process
82 system.cpu.createThreads()
H A Dse.py176 system = System(cpu = [CPUClass(cpu_id=i) for i in range(np)],
199 # If elastic tracing is enabled, then configure the cpu and attach the elastic
202 CpuConfig.config_etrace(CPUClass, system.cpu, options)
206 for cpu in system.cpu:
207 cpu.clk_domain = system.cpu_clk_domain
221 fatal("SimPoint/BPProbe should be done with an atomic cpu")
227 system.cpu[i].workload = multiprocesses
229 system.cpu[i].workload = multiprocesses[0]
231 system.cpu[
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/gem5/src/arch/arm/
H A DArmPMU.py102 cpu=None,
118 bpred = getattr(cpu, "branchPred", None) if cpu else None
128 self.addEvent(ProbeEvent(self,0x06, cpu, "RetiredLoads"))
129 self.addEvent(ProbeEvent(self,0x07, cpu, "RetiredStores"))
130 self.addEvent(ProbeEvent(self,0x08, cpu, "RetiredInsts"))
134 self.addEvent(ProbeEvent(self,0x0C, cpu, "RetiredBranches"))
139 self.addEvent(ProbeEvent(self, ARCH_EVENT_CORE_CYCLES, cpu,
142 self.addEvent(ProbeEvent(self,0x13, cpu, "RetiredLoads",

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