Lines Matching refs:cpu
52 #include "cpu/o3/thread_context.hh"
53 #include "cpu/quiesce_event.hh"
100 cpu->activateContext(thread->threadId());
113 if (cpu->isDraining()) {
122 cpu->suspendContext(thread->threadId());
142 cpu->addThreadToExitingList(thread->threadId());
188 cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));
203 cpu->isa[thread->threadId()]->clear();
210 return cpu->readArchIntReg(reg_idx, thread->threadId());
217 return cpu->readArchFloatReg(reg_idx, thread->threadId());
224 return cpu->readArchVecReg(reg_id, thread->threadId());
231 return cpu->getWritableArchVecReg(reg_id, thread->threadId());
239 return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
246 return cpu->readArchVecPredReg(reg_id, thread->threadId());
253 return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
260 return cpu->readArchCCReg(reg_idx, thread->threadId());
267 cpu->setArchIntReg(reg_idx, val, thread->threadId());
276 cpu->setArchFloatReg(reg_idx, val, thread->threadId());
286 cpu->setArchVecReg(reg_idx, val, thread->threadId());
296 cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
305 cpu->setArchVecPredReg(reg_idx, val, thread->threadId());
314 cpu->setArchCCReg(reg_idx, val, thread->threadId());
323 cpu->pcState(val, thread->threadId());
332 cpu->pcState(val, thread->threadId());
341 return cpu->isa[thread->threadId()]->flattenRegId(regId);
348 cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());
357 cpu->setMiscReg(misc_reg, val, thread->threadId());