Lines Matching refs:cpu

51 #include "cpu/o3/cpu.hh"
52 #include "cpu/o3/isa_specific.hh"
53 #include "cpu/base_dyn_inst.hh"
54 #include "cpu/inst_seq.hh"
55 #include "cpu/reg_class.hh"
83 InstSeqNum seq_num, O3CPU *cpu);
106 using BaseDynInst<Impl>::cpu;
142 return this->cpu->readMiscReg(misc_reg, this->threadNumber);
178 return this->cpu->readMiscReg(reg.index(), this->threadNumber);
199 // See cpu/o3/dyn_inst_impl.hh.
204 this->cpu->setMiscReg(
220 this->cpu->readIntReg(prev_phys_reg));
224 this->cpu->readFloatReg(prev_phys_reg));
228 this->cpu->readVecReg(prev_phys_reg));
232 this->cpu->readVecElem(prev_phys_reg));
236 this->cpu->readVecPredReg(prev_phys_reg));
240 this->cpu->readCCReg(prev_phys_reg));
273 return this->cpu->readIntReg(this->_srcRegIdx[idx]);
279 return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
285 return this->cpu->readVecReg(this->_srcRegIdx[idx]);
294 return this->cpu->getWritableVecReg(this->_destRegIdx[idx]);
303 return cpu->template readVecLane<uint8_t>(_srcRegIdx[idx]);
310 return cpu->template readVecLane<uint16_t>(_srcRegIdx[idx]);
317 return cpu->template readVecLane<uint32_t>(_srcRegIdx[idx]);
324 return cpu->template readVecLane<uint64_t>(_srcRegIdx[idx]);
332 return cpu->template setVecLane(_destRegIdx[idx], val);
362 return this->cpu->readVecElem(this->_srcRegIdx[idx]);
368 return this->cpu->readVecPredReg(this->_srcRegIdx[idx]);
374 return this->cpu->getWritableVecPredReg(this->_destRegIdx[idx]);
380 return this->cpu->readCCReg(this->_srcRegIdx[idx]);
389 this->cpu->setIntReg(this->_destRegIdx[idx], val);
396 this->cpu->setFloatReg(this->_destRegIdx[idx], val);
404 this->cpu->setVecReg(this->_destRegIdx[idx], val);
412 this->cpu->setVecElem(this->_destRegIdx[reg_idx], val);
420 this->cpu->setVecPredReg(this->_destRegIdx[idx], val);
426 this->cpu->setCCReg(this->_destRegIdx[idx], val);