Lines Matching refs:cpu
66 system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
79 for (i, cpu) in enumerate(system.cpu):
81 cpu.createInterruptController()
82 # Tie the cpu ports to the correct ruby system ports
83 cpu.icache_port = system.ruby._cpu_ports[i].slave
84 cpu.dcache_port = system.ruby._cpu_ports[i].slave
85 cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
86 cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
88 cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
89 cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
90 cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master