Searched refs:clock (Results 276 - 300 of 302) sorted by relevance

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/gem5/configs/learning_gem5/part2/
H A Dsimple_memobj.py47 # Set the clock fequency of the system (and all of its children)
49 system.clk_domain.clock = '1GHz'
/gem5/ext/sst/
H A Dgem5.cc80 TimeConverter *clock = registerClock( local
84 // This sets how many gem5 cycles we'll need to simulate per clock tick
85 sim_cycles = clock->getFactor();
172 m->clock();
/gem5/configs/example/
H A Dse.py187 # Create a source clock for the system and set the clock period
188 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
194 # Create a separate clock domain for the CPUs
195 system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
253 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Dfs.py114 # Create a source clock for the system and set the clock period
115 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
121 # Create a source clock for the CPUs and set the clock period
122 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
143 # For now, assign all the CPUs to the same clock domain
155 # Create a seperate clock domain for Ruby
156 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
185 # By default the IOCache runs at the system clock
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H A Dapu_se.py123 help="CPU clock")
125 help="GPU clock")
205 clock = options.GPUClock, variable
318 clock = options.CPUClock, variable
335 clock = options.CPUClock, variable
344 clock = options.CPUClock, variable
428 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
448 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
H A Dhmctest.py56 # set the clock fequency of the system
59 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
H A Dmemtest.py107 parser.add_option("--sys-clock", action="store", type="string",
109 help = """Top-level clock for blocks running at system
231 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
H A Dmemcheck.py106 parser.add_option("--sys-clock", action="store", type="string",
108 help = """Top-level clock for blocks running at system
226 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
/gem5/tests/configs/
H A Dbase_config.py177 # Create a seperate clock domain for Ruby
179 clock = options.ruby_clock,
192 # Create system clock domain. This provides clock value to every
194 # by a different clock domain.
196 system.clk_domain = SrcClockDomain(clock = '1GHz',
200 # Create a seperate clock domain for components that should
202 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
295 # create the iocache, which by default runs at the system clock
/gem5/configs/example/arm/
H A Ddevices.py125 self.clk_domain = SrcClockDomain(clock=cpu_clock,
194 self.clk_domain = SrcClockDomain(clock="1GHz",
280 key=lambda c: c.clk_domain.clock[0])
H A Dstarter_se.py97 # Create a voltage and clock domain for system components
99 self.clk_domain = SrcClockDomain(clock="1GHz",
/gem5/src/sim/
H A Dclock_domain.cc65 // Expose the current clock period as a stat for observability in
69 .name(params()->name + ".clock")
82 freqOpPoints(p->clock),
118 fatal("%s has a clock period of zero\n", name());
129 "Setting clock period to %d ticks for source clock %s\n",
163 // Integrated switching of the actual clock value, too
184 // Perform proper clock update when all related components have been
200 // Ensure that clock divider setting works as frequency divider and never
210 // update our clock perio
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/gem5/configs/learning_gem5/part1/
H A Dtwo_level.py86 # Set the clock fequency of the system (and all of its children)
88 system.clk_domain.clock = '1GHz'
/gem5/src/systemc/tests/systemc/datatypes/misc/concat/test02/
H A Dtest02.cpp191 sc_clock clock; local
193 x.clk(clock);
/gem5/src/systemc/tests/systemc/kernel/process_control/test03/
H A Dtest03.cpp342 sc_clock clock; local
346 dut.m_clk(clock);
/gem5/configs/common/
H A DHMC.py143 # own voltage and clock domains, different from the DRAM dies or from the
311 cd = SrcClockDomain(clock=clk, voltage_domain=vd)
351 # set the clock frequency for serial link
355 scd = SrcClockDomain(clock=clk, voltage_domain=vd)
415 scd = SrcClockDomain(clock=clk, voltage_domain=vd)
H A DFileSystemConfig.py60 size and the clock in /proc/cpuinfo if provided.
64 - /proc/cpuinfo which contains the clock and the L2 size
97 'cpu MHz : {clock:0.3f}\n' + \
111 # Note: it would be nice to use cpu.clock, but it hasn't
113 clock = cpu_clock,
/gem5/configs/dram/
H A Dsweep.py97 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
H A Dlow_power_sweep.py93 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
H A Dlat_mem_rd.py105 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
278 # note that everything is in the same clock domain, 2.0 GHz as
/gem5/tests/gem5/cpu_tests/
H A Drun.py125 system.clk_domain.clock = '1GHz'
/gem5/src/dev/arm/
H A DRealView.py233 # TODO: We currently don't have the notion of a clock source,
255 node.append(FdtPropertyWords("#clock-cells", [0]))
256 freq = int(1.0/self.freq.value) # Values are stored as a clock period
258 node.append(FdtPropertyStrings("clock-output-names",
367 # clk_domain can only store one clock (i.e. it is not a VectorParam)
372 node.append(FdtPropertyStrings("clock-names", ["uartclk", "apb_pclk"]))
418 clock = state.phandle(self.clk_domain.unproxy(self))
419 node.append(FdtPropertyWords("clocks", clock))
443 clock = state.phandle(self.clk_domain.unproxy(self))
444 node.append(FdtPropertyWords("clocks", clock))
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/gem5/src/gpu-compute/
H A Dshader.cc54 : ClockedObject(p), clock(p->clk_domain->clockPeriod()),
168 // clock all of the cu's
/gem5/src/cpu/
H A DBaseCPU.py328 freq = int(self.clk_domain.unproxy(self).clock[0].frequency)
329 node.append(FdtPropertyWords("clock-frequency", freq))
/gem5/src/systemc/tests/systemc/examples/aes/
H A Daes.cpp1057 sc_clock clock; local
1083 clock,
1094 clock,

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