112814Sandreas.sandberg@arm.com# Copyright (c) 2014-2015, 2018 ARM Limited 210139Sandreas.hansson@arm.com# All rights reserved. 310139Sandreas.hansson@arm.com# 410139Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 510139Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 610139Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 710139Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 810139Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 910139Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 1010139Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 1110139Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 1210139Sandreas.hansson@arm.com# 1310139Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 1410139Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 1510139Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 1610139Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 1710139Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 1810139Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 1910139Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 2010139Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 2110139Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 2210139Sandreas.hansson@arm.com# this software without specific prior written permission. 2310139Sandreas.hansson@arm.com# 2410139Sandreas.hansson@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510139Sandreas.hansson@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610139Sandreas.hansson@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710139Sandreas.hansson@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810139Sandreas.hansson@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910139Sandreas.hansson@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010139Sandreas.hansson@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3110139Sandreas.hansson@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3210139Sandreas.hansson@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310139Sandreas.hansson@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410139Sandreas.hansson@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510139Sandreas.hansson@arm.com# 3610139Sandreas.hansson@arm.com# Authors: Andreas Hansson 3710139Sandreas.hansson@arm.com 3812564Sgabeblack@google.comfrom __future__ import print_function 3913774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 4012564Sgabeblack@google.com 4112814Sandreas.sandberg@arm.comimport math 4210139Sandreas.hansson@arm.comimport optparse 4310139Sandreas.hansson@arm.com 4410139Sandreas.hansson@arm.comimport m5 4510139Sandreas.hansson@arm.comfrom m5.objects import * 4610139Sandreas.hansson@arm.comfrom m5.util import addToPath 4711766Sandreas.sandberg@arm.comfrom m5.stats import periodicStatDump 4810139Sandreas.hansson@arm.com 4911682Sandreas.hansson@arm.comaddToPath('../') 5010139Sandreas.hansson@arm.com 5111682Sandreas.hansson@arm.comfrom common import MemConfig 5210139Sandreas.hansson@arm.com 5310139Sandreas.hansson@arm.com# this script is helpful to sweep the efficiency of a specific memory 5410139Sandreas.hansson@arm.com# controller configuration, by varying the number of banks accessed, 5510139Sandreas.hansson@arm.com# and the sequential stride size (how many bytes per activate), and 5610139Sandreas.hansson@arm.com# observe what bus utilisation (bandwidth) is achieved 5710139Sandreas.hansson@arm.com 5810139Sandreas.hansson@arm.comparser = optparse.OptionParser() 5910139Sandreas.hansson@arm.com 6012814Sandreas.sandberg@arm.comdram_generators = { 6112814Sandreas.sandberg@arm.com "DRAM" : lambda x: x.createDram, 6212814Sandreas.sandberg@arm.com "DRAM_ROTATE" : lambda x: x.createDramRot, 6312814Sandreas.sandberg@arm.com} 6412814Sandreas.sandberg@arm.com 6511837Swendy.elsasser@arm.com# Use a single-channel DDR3-1600 x64 (8x8 topology) by default 6611837Swendy.elsasser@arm.comparser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", 6710139Sandreas.hansson@arm.com choices=MemConfig.mem_names(), 6810139Sandreas.hansson@arm.com help = "type of memory to use") 6910139Sandreas.hansson@arm.com 7010743Sandreas.hansson@arm.comparser.add_option("--mem-ranks", "-r", type="int", default=1, 7110392Swendy.elsasser@arm.com help = "Number of ranks to iterate across") 7210392Swendy.elsasser@arm.com 7310392Swendy.elsasser@arm.comparser.add_option("--rd_perc", type="int", default=100, 7410392Swendy.elsasser@arm.com help = "Percentage of read commands") 7510392Swendy.elsasser@arm.com 7610392Swendy.elsasser@arm.comparser.add_option("--mode", type="choice", default="DRAM", 7712814Sandreas.sandberg@arm.com choices=dram_generators.keys(), 7810392Swendy.elsasser@arm.com help = "DRAM: Random traffic; \ 7910392Swendy.elsasser@arm.com DRAM_ROTATE: Traffic rotating across banks and ranks") 8010392Swendy.elsasser@arm.com 8110392Swendy.elsasser@arm.comparser.add_option("--addr_map", type="int", default=1, 8210392Swendy.elsasser@arm.com help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 8310392Swendy.elsasser@arm.com 8410139Sandreas.hansson@arm.com(options, args) = parser.parse_args() 8510139Sandreas.hansson@arm.com 8610139Sandreas.hansson@arm.comif args: 8712564Sgabeblack@google.com print("Error: script doesn't take any positional arguments") 8810139Sandreas.hansson@arm.com sys.exit(1) 8910139Sandreas.hansson@arm.com 9010139Sandreas.hansson@arm.com# at the moment we stay with the default open-adaptive page policy, 9110139Sandreas.hansson@arm.com# and address mapping 9210139Sandreas.hansson@arm.com 9311125Sandreas.hansson@arm.com# start with the system itself, using a multi-layer 2.0 GHz 9411125Sandreas.hansson@arm.com# crossbar, delivering 64 bytes / 3 cycles (one header cycle) 9511125Sandreas.hansson@arm.com# which amounts to 42.7 GByte/s per layer and thus per port 9611125Sandreas.hansson@arm.comsystem = System(membus = IOXBar(width = 32)) 9711125Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = '2.0GHz', 9810139Sandreas.hansson@arm.com voltage_domain = 9910139Sandreas.hansson@arm.com VoltageDomain(voltage = '1V')) 10010139Sandreas.hansson@arm.com 10110139Sandreas.hansson@arm.com# we are fine with 256 MB memory for now 10210139Sandreas.hansson@arm.commem_range = AddrRange('256MB') 10310139Sandreas.hansson@arm.comsystem.mem_ranges = [mem_range] 10410139Sandreas.hansson@arm.com 10510833Sandreas.hansson@arm.com# do not worry about reserving space for the backing store 10611223Sandreas.hansson@arm.comsystem.mmap_using_noreserve = True 10710833Sandreas.hansson@arm.com 10810139Sandreas.hansson@arm.com# force a single channel to match the assumptions in the DRAM traffic 10910139Sandreas.hansson@arm.com# generator 11010139Sandreas.hansson@arm.comoptions.mem_channels = 1 11110832Swendy.elsasser@arm.comoptions.external_memory_system = 0 11211125Sandreas.hansson@arm.comoptions.tlm_memory = 0 11311251Sradhika.jagtap@ARM.comoptions.elastic_trace_en = 0 11410139Sandreas.hansson@arm.comMemConfig.config_mem(options, system) 11510139Sandreas.hansson@arm.com 11610139Sandreas.hansson@arm.com# the following assumes that we are using the native DRAM 11710139Sandreas.hansson@arm.com# controller, check to be sure 11810146Sandreas.hansson@arm.comif not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 11910146Sandreas.hansson@arm.com fatal("This script assumes the memory is a DRAMCtrl subclass") 12010139Sandreas.hansson@arm.com 12110833Sandreas.hansson@arm.com# there is no point slowing things down by saving any data 12210833Sandreas.hansson@arm.comsystem.mem_ctrls[0].null = True 12310833Sandreas.hansson@arm.com 12410392Swendy.elsasser@arm.com# Set the address mapping based on input argument 12510392Swendy.elsasser@arm.com# Default to RoRaBaCoCh 12610392Swendy.elsasser@arm.comif options.addr_map == 0: 12710392Swendy.elsasser@arm.com system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh" 12810392Swendy.elsasser@arm.comelif options.addr_map == 1: 12910392Swendy.elsasser@arm.com system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 13010392Swendy.elsasser@arm.comelse: 13110392Swendy.elsasser@arm.com fatal("Did not specify a valid address map argument") 13210139Sandreas.hansson@arm.com 13310139Sandreas.hansson@arm.com# stay in each state for 0.25 ms, long enough to warm things up, and 13410139Sandreas.hansson@arm.com# short enough to avoid hitting a refresh 13510139Sandreas.hansson@arm.comperiod = 250000000 13610139Sandreas.hansson@arm.com 13710139Sandreas.hansson@arm.com# stay in each state as long as the dump/reset period, use the entire 13810139Sandreas.hansson@arm.com# range, issue transactions of the right DRAM burst size, and match 13910139Sandreas.hansson@arm.com# the DRAM maximum bandwidth to ensure that it is saturated 14010139Sandreas.hansson@arm.com 14110139Sandreas.hansson@arm.com# get the number of banks 14210139Sandreas.hansson@arm.comnbr_banks = system.mem_ctrls[0].banks_per_rank.value 14310139Sandreas.hansson@arm.com 14410139Sandreas.hansson@arm.com# determine the burst length in bytes 14510139Sandreas.hansson@arm.comburst_size = int((system.mem_ctrls[0].devices_per_rank.value * 14610139Sandreas.hansson@arm.com system.mem_ctrls[0].device_bus_width.value * 14710139Sandreas.hansson@arm.com system.mem_ctrls[0].burst_length.value) / 8) 14810139Sandreas.hansson@arm.com 14910139Sandreas.hansson@arm.com# next, get the page size in bytes 15010139Sandreas.hansson@arm.compage_size = system.mem_ctrls[0].devices_per_rank.value * \ 15110139Sandreas.hansson@arm.com system.mem_ctrls[0].device_rowbuffer_size.value 15210139Sandreas.hansson@arm.com 15311223Sandreas.hansson@arm.com# match the maximum bandwidth of the memory, the parameter is in seconds 15411223Sandreas.hansson@arm.com# and we need it in ticks (ps) 15510139Sandreas.hansson@arm.comitt = system.mem_ctrls[0].tBURST.value * 1000000000000 15610139Sandreas.hansson@arm.com 15710139Sandreas.hansson@arm.com# assume we start at 0 15810139Sandreas.hansson@arm.commax_addr = mem_range.end 15910139Sandreas.hansson@arm.com 16010323Sandreas.hansson@arm.com# use min of the page size and 512 bytes as that should be more than 16110323Sandreas.hansson@arm.com# enough 16210323Sandreas.hansson@arm.commax_stride = min(512, page_size) 16310323Sandreas.hansson@arm.com 16410139Sandreas.hansson@arm.com# create a traffic generator, and point it to the file we just created 16512814Sandreas.sandberg@arm.comsystem.tgen = PyTrafficGen() 16610139Sandreas.hansson@arm.com 16710139Sandreas.hansson@arm.com# add a communication monitor 16810139Sandreas.hansson@arm.comsystem.monitor = CommMonitor() 16910139Sandreas.hansson@arm.com 17010139Sandreas.hansson@arm.com# connect the traffic generator to the bus via a communication monitor 17110139Sandreas.hansson@arm.comsystem.tgen.port = system.monitor.slave 17210139Sandreas.hansson@arm.comsystem.monitor.master = system.membus.slave 17310139Sandreas.hansson@arm.com 17410139Sandreas.hansson@arm.com# connect the system port even if it is not used in this example 17510139Sandreas.hansson@arm.comsystem.system_port = system.membus.slave 17610139Sandreas.hansson@arm.com 17710139Sandreas.hansson@arm.com# every period, dump and reset all stats 17810139Sandreas.hansson@arm.comperiodicStatDump(period) 17910139Sandreas.hansson@arm.com 18010139Sandreas.hansson@arm.com# run Forrest, run! 18110139Sandreas.hansson@arm.comroot = Root(full_system = False, system = system) 18210139Sandreas.hansson@arm.comroot.system.mem_mode = 'timing' 18310139Sandreas.hansson@arm.com 18410139Sandreas.hansson@arm.comm5.instantiate() 18512814Sandreas.sandberg@arm.com 18612814Sandreas.sandberg@arm.comdef trace(): 18712814Sandreas.sandberg@arm.com generator = dram_generators[options.mode](system.tgen) 18812814Sandreas.sandberg@arm.com for bank in range(1, nbr_banks + 1): 18912814Sandreas.sandberg@arm.com for stride_size in range(burst_size, max_stride + 1, burst_size): 19012814Sandreas.sandberg@arm.com num_seq_pkts = int(math.ceil(float(stride_size) / burst_size)) 19112814Sandreas.sandberg@arm.com yield generator(period, 19212814Sandreas.sandberg@arm.com 0, max_addr, burst_size, int(itt), int(itt), 19312814Sandreas.sandberg@arm.com options.rd_perc, 0, 19412814Sandreas.sandberg@arm.com num_seq_pkts, page_size, nbr_banks, bank, 19512814Sandreas.sandberg@arm.com options.addr_map, options.mem_ranks) 19612814Sandreas.sandberg@arm.com yield system.tgen.createExit(0) 19712814Sandreas.sandberg@arm.com 19812814Sandreas.sandberg@arm.comsystem.tgen.start(trace()) 19912814Sandreas.sandberg@arm.com 20012814Sandreas.sandberg@arm.comm5.simulate() 20110323Sandreas.hansson@arm.com 20212564Sgabeblack@google.comprint("DRAM sweep with burst: %d, banks: %d, max stride: %d" % 20312564Sgabeblack@google.com (burst_size, nbr_banks, max_stride)) 204