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13774:a1be2a0c55f2 |
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25-Feb-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
configs: Use absolute import paths
Use absoluate import paths to be Python 3 compatible. This also imports absolute_import from __future__ to ensure that Python 2.7 behaves the same way as Python 3.
Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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12814:074f6240ff4c |
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27-Apr-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
configs: Update the DRAM sweep script to use PyTrafficGen
Instead of generating a text configuration, use the new Python-based traffic generator.
Change-Id: I6fb88ec45b74bb87470aa265af18b5a2ff24c314 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11519 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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12564:2778478ca882 |
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06-Mar-2018 |
Gabe Black <gabeblack@google.com> |
config: Switch from the print statement to the print function.
Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0 Reviewed-on: https://gem5-review.googlesource.com/8762 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
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11837:17b37f38944a |
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14-Feb-2017 |
Wendy Elsasser <wendy.elsasser@arm.com> |
mem: Update DRAM configuration names
Names of DRAM configurations were updated to reflect both the channel and device data width.
Previous naming format was: <DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>
The following nomenclature is now used: <DEVICE_TYPE>_<DATA_RATE>_<n>x<w> where n = The number of devices per rank on the channel x = Device width
Total channel width can be calculated by n*w
Example: A 64-bit DDR4, 2400 channel consisting of 4-bit devices: n = 16 w = 4 The resulting configuration name is: DDR4_2400_16x4
Updated scripts to match new naming convention.
Added unique configurations for DDR4 for: 1) 16x4 2) 8x8 3) 4x16
Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1 Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
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11766:7c95caf53250 |
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19-Dec-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
python: Export periodicStatDump
Some configuration scripts need periodic stat dumps. One of the ways this can be achieved is by using the pariodicStatDump helper function. This function was previously only exported in the internal name space. Export it as a normal function in m5.stat instead.
Change-Id: Ic88bf1fd33042a62ab436d5944d8ed778264ac98 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
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11682:612f75cf36a0 |
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14-Oct-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Make configs/common a Python package
Continue along the same line as the recent patch that made the Ruby-related config scripts Python packages and make also the configs/common directory a package.
All affected config scripts are updated (hopefully).
Note that this change makes it apparent that the current organisation and naming of the config directory and its subdirectories is rather chaotic. We mix scripts that are directly invoked with scripts that merely contain convenience functions. While it is not addressed in this patch we should follow up with a re-organisation of the config structure, and renaming of some of the packages.
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11251:a15c86af004a |
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07-Dec-2015 |
Radhika Jagtap <radhika.jagtap@ARM.com> |
config: Enable elastic trace capture and replay in se/fs
This patch adds changes to the configuration scripts to support elastic tracing and replay.
The patch adds a command line option to enable elastic tracing in SE mode and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out both instruction fetch and data dependency traces. The patch also enables configuring the TraceCPU to replay traces using the SE and FS script.
The replay run is designed to resume from checkpoint using atomic cpu to restore state keeping it consistent with FS run flow. It then switches to TraceCPU to replay the input traces.
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11223:2981e399c816 |
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22-Nov-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Minor fixes to the DRAM utilisation sweep
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11125:f918d72dbc02 |
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25-Sep-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
util: Fix minor issues in DRAM sweep scripts
This patch fixes a few issues in the sweep scripts, bringing them up-to-date with the latest memory configs and options.
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10833:a4a2ba97a654 |
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15-May-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Use null memory for DRAM sweep script
Do not waste time when we do not care about the data.
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10832:33f1c7b65a88 |
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15-May-2015 |
Wendy Elsasser <wendy.elsasser@arm.com> |
config: Add new MemConfig options to DRAM sweep script
Update script to match current MemConfig options with external_memory_system option set to 0.
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10789:e94c22bd9ef1 |
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20-Apr-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Remove memory aliases and rely on class name
Instead of maintaining two lists, rely entirely on the class name. There is really no point in causing unecessary confusion.
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10743:062c820aef24 |
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19-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Fix DRAM rank option in sweep script
Align with changes in the common bits.
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10720:67b3e74de9ae |
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02-Mar-2015 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and NoncoherentXBar to distinguish the different uses in the system. We use the crossbar in a wide range of places: interfacing cores to the L2, as a system interconnect, connecting I/O and peripherals, etc. Needless to say, these crossbars have very different performance, and the clock frequency alone is not enough to distinguish these scenarios.
Instead of trying to capture every possible case, this patch introduces dedicated subclasses for the three primary use-cases: L2XBar, SystemXBar and IOXbar. More can be added if needed, and the defaults can be overridden.
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10405:7a618c07e663 |
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20-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Rename Bus to XBar to better reflect its behaviour
This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus.
As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet.
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10392:0100f00a229e |
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20-Sep-2014 |
Wendy Elsasser <wendy.elsasser@arm.com> |
cpu: Update DRAM traffic gen
Add new DRAM_ROTATE mode to traffic generator. This mode will generate DRAM traffic that rotates across banks per rank, command types, and ranks per channel
The looping order is illustrated below: for (ranks per channel) for (command types) for (banks per rank) // Generate DRAM Command Series
This patch also adds the read percentage as an input argument to the DRAM sweep script. If the simulated read percentage is 0 or 100, the middle for loop does not generate additional commands. This loop is used only when the read percentage is set to 50, in which case the middle loop will toggle between read and write commands.
Modified sweep.py script, which generates DRAM traffic. Added input arguments and support for new DRAM_ROTATE mode. The script now has input arguments for: 1) Read percentage 2) Number of ranks 3) Address mapping 4) Traffic generator mode (DRAM or DRAM_ROTATE)
The default values are: 100% reads, 1 rank, RoRaBaCoCh address mapping, and DRAM traffic gen mode
For the DRAM traffic mode, added multi-rank support.
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10323:5169ebd26163 |
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03-Sep-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Add utility script to plot DRAM efficiency sweep
This patch adds basic functionality to quickly visualise the output from the DRAM efficiency script. There are some unfortunate hacks needed to communicate the needed information from one script to the other, and we fall back on (ab)using the simout to do this.
As part of this patch we also trim the efficiency sweep to stop at 512 bytes as this should be sufficient for all forseeable DRAMs.
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10219:4161cfba9658 |
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09-May-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Bump DRAM sweep bus speed to match DDR4 config
This patch bumps the bus clock speed such that the interconnect does not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2 GByte/s theoretical max.
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10146:27dfed4c8403 |
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23-Mar-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
This patch renames the not-so-simple SimpleDRAM to a more suitable DRAMCtrl. The name change is intended to ensure that we do not send the wrong message (although the "simple" in SimpleDRAM was originally intended as in cleverly simple, or elegant).
As the DRAM controller modelling work is being presented at ISPASS'14 our hope is that a broader audience will use the model in the future.
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10139:45d16673b95a |
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23-Mar-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Add a DRAM efficiency-sweep script
This patch adds a configuration that simplifies evaluation of DRAM controller configurations by automating a sweep of stride size and bank parallelism. It works in a rather unconventional way, as it needs to print the traffic generator stimuli based on the memory organisation. Hence, it starts by configuring the memory, then it prints a traffic-generator config file, and loads it.
The resulting stats have one period per data point, identified by the stride size, and the number of banks being used.
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