sweep.py revision 10743:062c820aef24
16757SAli.Saidi@ARM.com# Copyright (c) 2014-2015 ARM Limited 210338SCurtis.Dunham@arm.com# All rights reserved. 36757SAli.Saidi@ARM.com# 46757SAli.Saidi@ARM.com# The license below extends only to copyright in the software and shall 57111Sgblack@eecs.umich.edu# not be construed as granting a license to any other intellectual 67111Sgblack@eecs.umich.edu# property including but not limited to intellectual property relating 77111Sgblack@eecs.umich.edu# to a hardware implementation of the functionality of the software 87111Sgblack@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 97111Sgblack@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 107111Sgblack@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 117111Sgblack@eecs.umich.edu# modified or unmodified, in source code or in binary form. 127111Sgblack@eecs.umich.edu# 137111Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 146757SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 156757SAli.Saidi@ARM.com# met: redistributions of source code must retain the above copyright 166757SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 176757SAli.Saidi@ARM.com# redistributions in binary form must reproduce the above copyright 186757SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer in the 196757SAli.Saidi@ARM.com# documentation and/or other materials provided with the distribution; 206757SAli.Saidi@ARM.com# neither the name of the copyright holders nor the names of its 216757SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 226757SAli.Saidi@ARM.com# this software without specific prior written permission. 236757SAli.Saidi@ARM.com# 246757SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 256757SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 266757SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 276757SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 286757SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 296757SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 306757SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 316757SAli.Saidi@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 326757SAli.Saidi@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 336757SAli.Saidi@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 346757SAli.Saidi@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 356757SAli.Saidi@ARM.com# 366757SAli.Saidi@ARM.com# Authors: Andreas Hansson 376757SAli.Saidi@ARM.com 386757SAli.Saidi@ARM.comimport optparse 396735Sgblack@eecs.umich.edu 4010474Sandreas.hansson@arm.comimport m5 416757SAli.Saidi@ARM.comfrom m5.objects import * 426757SAli.Saidi@ARM.comfrom m5.util import addToPath 437707Sgblack@eecs.umich.edufrom m5.internal.stats import periodicStatDump 4410037SARM gem5 Developers 458782Sgblack@eecs.umich.eduaddToPath('../common') 466757SAli.Saidi@ARM.com 478782Sgblack@eecs.umich.eduimport MemConfig 488887Sgeoffrey.blake@arm.com 498886SAli.Saidi@ARM.com# this script is helpful to sweep the efficiency of a specific memory 506757SAli.Saidi@ARM.com# controller configuration, by varying the number of banks accessed, 518706Sandreas.hansson@arm.com# and the sequential stride size (how many bytes per activate), and 528782Sgblack@eecs.umich.edu# observe what bus utilisation (bandwidth) is achieved 537749SAli.Saidi@ARM.com 546735Sgblack@eecs.umich.eduparser = optparse.OptionParser() 556735Sgblack@eecs.umich.edu 566735Sgblack@eecs.umich.edu# Use a single-channel DDR3-1600 x64 by default 576735Sgblack@eecs.umich.eduparser.add_option("--mem-type", type="choice", default="ddr3_1600_x64", 586735Sgblack@eecs.umich.edu choices=MemConfig.mem_names(), 596735Sgblack@eecs.umich.edu help = "type of memory to use") 609058Satgutier@umich.edu 616735Sgblack@eecs.umich.eduparser.add_option("--mem-ranks", "-r", type="int", default=1, 628886SAli.Saidi@ARM.com help = "Number of ranks to iterate across") 6310474Sandreas.hansson@arm.com 648286SAli.Saidi@ARM.comparser.add_option("--rd_perc", type="int", default=100, 656735Sgblack@eecs.umich.edu help = "Percentage of read commands") 666735Sgblack@eecs.umich.edu 677707Sgblack@eecs.umich.eduparser.add_option("--mode", type="choice", default="DRAM", 687707Sgblack@eecs.umich.edu choices=["DRAM", "DRAM_ROTATE"], 697707Sgblack@eecs.umich.edu help = "DRAM: Random traffic; \ 708806Sgblack@eecs.umich.edu DRAM_ROTATE: Traffic rotating across banks and ranks") 718806Sgblack@eecs.umich.edu 728806Sgblack@eecs.umich.eduparser.add_option("--addr_map", type="int", default=1, 738806Sgblack@eecs.umich.edu help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 748706Sandreas.hansson@arm.com 757693SAli.Saidi@ARM.com(options, args) = parser.parse_args() 767693SAli.Saidi@ARM.com 777693SAli.Saidi@ARM.comif args: 7810037SARM gem5 Developers print "Error: script doesn't take any positional arguments" 7910037SARM gem5 Developers sys.exit(1) 8010037SARM gem5 Developers 8110037SARM gem5 Developers# at the moment we stay with the default open-adaptive page policy, 8210037SARM gem5 Developers# and address mapping 8310037SARM gem5 Developers 847693SAli.Saidi@ARM.com# start with the system itself, using a multi-layer 1.5 GHz 8510037SARM gem5 Developers# crossbar, delivering 64 bytes / 5 cycles (one header cycle) 867693SAli.Saidi@ARM.com# which amounts to 19.2 GByte/s per layer and thus per port 877693SAli.Saidi@ARM.comsystem = System(membus = IOXBar(width = 16)) 8810037SARM gem5 Developerssystem.clk_domain = SrcClockDomain(clock = '1.5GHz', 8910318Sandreas.hansson@arm.com voltage_domain = 9010037SARM gem5 Developers VoltageDomain(voltage = '1V')) 9110037SARM gem5 Developers 9210037SARM gem5 Developers# we are fine with 256 MB memory for now 9310037SARM gem5 Developersmem_range = AddrRange('256MB') 9410037SARM gem5 Developerssystem.mem_ranges = [mem_range] 9510037SARM gem5 Developers 9610037SARM gem5 Developers# force a single channel to match the assumptions in the DRAM traffic 9710037SARM gem5 Developers# generator 9810037SARM gem5 Developersoptions.mem_channels = 1 9910037SARM gem5 DevelopersMemConfig.config_mem(options, system) 10010037SARM gem5 Developers 10110037SARM gem5 Developers# the following assumes that we are using the native DRAM 10210037SARM gem5 Developers# controller, check to be sure 10310037SARM gem5 Developersif not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 10410037SARM gem5 Developers fatal("This script assumes the memory is a DRAMCtrl subclass") 10510037SARM gem5 Developers 10610037SARM gem5 Developers# Set the address mapping based on input argument 10710037SARM gem5 Developers# Default to RoRaBaCoCh 10810037SARM gem5 Developersif options.addr_map == 0: 10910037SARM gem5 Developers system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh" 11010037SARM gem5 Developerselif options.addr_map == 1: 11110037SARM gem5 Developers system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 11210037SARM gem5 Developerselse: 11310037SARM gem5 Developers fatal("Did not specify a valid address map argument") 11410037SARM gem5 Developers 11510037SARM gem5 Developers# stay in each state for 0.25 ms, long enough to warm things up, and 11610037SARM gem5 Developers# short enough to avoid hitting a refresh 11710037SARM gem5 Developersperiod = 250000000 1187693SAli.Saidi@ARM.com 11910037SARM gem5 Developers# this is where we go off piste, and print the traffic generator 12010037SARM gem5 Developers# configuration that we will later use, crazy but it works 12110037SARM gem5 Developerscfg_file_name = "configs/dram/sweep.cfg" 12210037SARM gem5 Developerscfg_file = open(cfg_file_name, 'w') 12310037SARM gem5 Developers 1247693SAli.Saidi@ARM.com# stay in each state as long as the dump/reset period, use the entire 1257650SAli.Saidi@ARM.com# range, issue transactions of the right DRAM burst size, and match 12610037SARM gem5 Developers# the DRAM maximum bandwidth to ensure that it is saturated 1276757SAli.Saidi@ARM.com 1286757SAli.Saidi@ARM.com# get the number of banks 1297693SAli.Saidi@ARM.comnbr_banks = system.mem_ctrls[0].banks_per_rank.value 1307693SAli.Saidi@ARM.com 1317693SAli.Saidi@ARM.com# determine the burst length in bytes 1329920Syasuko.eckert@amd.comburst_size = int((system.mem_ctrls[0].devices_per_rank.value * 13310037SARM gem5 Developers system.mem_ctrls[0].device_bus_width.value * 13410037SARM gem5 Developers system.mem_ctrls[0].burst_length.value) / 8) 13510037SARM gem5 Developers 13610037SARM gem5 Developers# next, get the page size in bytes 13710037SARM gem5 Developerspage_size = system.mem_ctrls[0].devices_per_rank.value * \ 1388887Sgeoffrey.blake@arm.com system.mem_ctrls[0].device_rowbuffer_size.value 1398887Sgeoffrey.blake@arm.com 1408887Sgeoffrey.blake@arm.com# match the maximum bandwidth of the memory, the parameter is in ns 1418887Sgeoffrey.blake@arm.com# and we need it in ticks 1428887Sgeoffrey.blake@arm.comitt = system.mem_ctrls[0].tBURST.value * 1000000000000 1438887Sgeoffrey.blake@arm.com 1448887Sgeoffrey.blake@arm.com# assume we start at 0 1457693SAli.Saidi@ARM.commax_addr = mem_range.end 1467693SAli.Saidi@ARM.com 1477748SAli.Saidi@ARM.com# use min of the page size and 512 bytes as that should be more than 1487748SAli.Saidi@ARM.com# enough 1497748SAli.Saidi@ARM.commax_stride = min(512, page_size) 1509920Syasuko.eckert@amd.com 1519431SAndreas.Sandberg@ARM.com# now we create the state by iterating over the stride size from burst 1528208SAli.Saidi@ARM.com# size to the max stride, and from using only a single bank up to the 1539920Syasuko.eckert@amd.com# number of banks available 1549431SAndreas.Sandberg@ARM.comnxt_state = 0 1558208SAli.Saidi@ARM.comfor bank in range(1, nbr_banks + 1): 15610338SCurtis.Dunham@arm.com for stride_size in range(burst_size, max_stride + 1, burst_size): 15710338SCurtis.Dunham@arm.com cfg_file.write("STATE %d %d %s %d 0 %d %d " 1589920Syasuko.eckert@amd.com "%d %d %d %d %d %d %d %d %d\n" % 1599920Syasuko.eckert@amd.com (nxt_state, period, options.mode, options.rd_perc, 1607748SAli.Saidi@ARM.com max_addr, burst_size, itt, itt, 0, stride_size, 1616759SAli.Saidi@ARM.com page_size, nbr_banks, bank, options.addr_map, 1627748SAli.Saidi@ARM.com options.mem_ranks)) 1637748SAli.Saidi@ARM.com nxt_state = nxt_state + 1 1647748SAli.Saidi@ARM.com 1657748SAli.Saidi@ARM.comcfg_file.write("INIT 0\n") 1667749SAli.Saidi@ARM.com 1677748SAli.Saidi@ARM.com# go through the states one by one 1687749SAli.Saidi@ARM.comfor state in range(1, nxt_state): 1697749SAli.Saidi@ARM.com cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 1707749SAli.Saidi@ARM.com 1717749SAli.Saidi@ARM.comcfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 1726759SAli.Saidi@ARM.com 1737752SWilliam.Wang@arm.comcfg_file.close() 17410037SARM gem5 Developers 17510037SARM gem5 Developers# create a traffic generator, and point it to the file we just created 17610037SARM gem5 Developerssystem.tgen = TrafficGen(config_file = cfg_file_name) 17710037SARM gem5 Developers 17810037SARM gem5 Developers# add a communication monitor 17910037SARM gem5 Developerssystem.monitor = CommMonitor() 18010037SARM gem5 Developers 18110037SARM gem5 Developers# connect the traffic generator to the bus via a communication monitor 18210037SARM gem5 Developerssystem.tgen.port = system.monitor.slave 18310037SARM gem5 Developerssystem.monitor.master = system.membus.slave 18410037SARM gem5 Developers 18510037SARM gem5 Developers# connect the system port even if it is not used in this example 18610037SARM gem5 Developerssystem.system_port = system.membus.slave 18710037SARM gem5 Developers 18810037SARM gem5 Developers# every period, dump and reset all stats 18910037SARM gem5 DevelopersperiodicStatDump(period) 19010037SARM gem5 Developers 19110037SARM gem5 Developers# run Forrest, run! 19210037SARM gem5 Developersroot = Root(full_system = False, system = system) 19310037SARM gem5 Developersroot.system.mem_mode = 'timing' 19410037SARM gem5 Developers 19510037SARM gem5 Developersm5.instantiate() 19610037SARM gem5 Developersm5.simulate(nxt_state * period) 19710037SARM gem5 Developers 19810037SARM gem5 Developersprint "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \ 19910037SARM gem5 Developers (burst_size, nbr_banks, max_stride) 20010190Sakash.bagdia@arm.com