sweep.py revision 12564:2778478ca882
1# Copyright (c) 2014-2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37 38from __future__ import print_function 39 40import optparse 41 42import m5 43from m5.objects import * 44from m5.util import addToPath 45from m5.stats import periodicStatDump 46 47addToPath('../') 48 49from common import MemConfig 50 51# this script is helpful to sweep the efficiency of a specific memory 52# controller configuration, by varying the number of banks accessed, 53# and the sequential stride size (how many bytes per activate), and 54# observe what bus utilisation (bandwidth) is achieved 55 56parser = optparse.OptionParser() 57 58# Use a single-channel DDR3-1600 x64 (8x8 topology) by default 59parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", 60 choices=MemConfig.mem_names(), 61 help = "type of memory to use") 62 63parser.add_option("--mem-ranks", "-r", type="int", default=1, 64 help = "Number of ranks to iterate across") 65 66parser.add_option("--rd_perc", type="int", default=100, 67 help = "Percentage of read commands") 68 69parser.add_option("--mode", type="choice", default="DRAM", 70 choices=["DRAM", "DRAM_ROTATE"], 71 help = "DRAM: Random traffic; \ 72 DRAM_ROTATE: Traffic rotating across banks and ranks") 73 74parser.add_option("--addr_map", type="int", default=1, 75 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 76 77(options, args) = parser.parse_args() 78 79if args: 80 print("Error: script doesn't take any positional arguments") 81 sys.exit(1) 82 83# at the moment we stay with the default open-adaptive page policy, 84# and address mapping 85 86# start with the system itself, using a multi-layer 2.0 GHz 87# crossbar, delivering 64 bytes / 3 cycles (one header cycle) 88# which amounts to 42.7 GByte/s per layer and thus per port 89system = System(membus = IOXBar(width = 32)) 90system.clk_domain = SrcClockDomain(clock = '2.0GHz', 91 voltage_domain = 92 VoltageDomain(voltage = '1V')) 93 94# we are fine with 256 MB memory for now 95mem_range = AddrRange('256MB') 96system.mem_ranges = [mem_range] 97 98# do not worry about reserving space for the backing store 99system.mmap_using_noreserve = True 100 101# force a single channel to match the assumptions in the DRAM traffic 102# generator 103options.mem_channels = 1 104options.external_memory_system = 0 105options.tlm_memory = 0 106options.elastic_trace_en = 0 107MemConfig.config_mem(options, system) 108 109# the following assumes that we are using the native DRAM 110# controller, check to be sure 111if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 112 fatal("This script assumes the memory is a DRAMCtrl subclass") 113 114# there is no point slowing things down by saving any data 115system.mem_ctrls[0].null = True 116 117# Set the address mapping based on input argument 118# Default to RoRaBaCoCh 119if options.addr_map == 0: 120 system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh" 121elif options.addr_map == 1: 122 system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 123else: 124 fatal("Did not specify a valid address map argument") 125 126# stay in each state for 0.25 ms, long enough to warm things up, and 127# short enough to avoid hitting a refresh 128period = 250000000 129 130# this is where we go off piste, and print the traffic generator 131# configuration that we will later use, crazy but it works 132cfg_file_name = "configs/dram/sweep.cfg" 133cfg_file = open(cfg_file_name, 'w') 134 135# stay in each state as long as the dump/reset period, use the entire 136# range, issue transactions of the right DRAM burst size, and match 137# the DRAM maximum bandwidth to ensure that it is saturated 138 139# get the number of banks 140nbr_banks = system.mem_ctrls[0].banks_per_rank.value 141 142# determine the burst length in bytes 143burst_size = int((system.mem_ctrls[0].devices_per_rank.value * 144 system.mem_ctrls[0].device_bus_width.value * 145 system.mem_ctrls[0].burst_length.value) / 8) 146 147# next, get the page size in bytes 148page_size = system.mem_ctrls[0].devices_per_rank.value * \ 149 system.mem_ctrls[0].device_rowbuffer_size.value 150 151# match the maximum bandwidth of the memory, the parameter is in seconds 152# and we need it in ticks (ps) 153itt = system.mem_ctrls[0].tBURST.value * 1000000000000 154 155# assume we start at 0 156max_addr = mem_range.end 157 158# use min of the page size and 512 bytes as that should be more than 159# enough 160max_stride = min(512, page_size) 161 162# now we create the state by iterating over the stride size from burst 163# size to the max stride, and from using only a single bank up to the 164# number of banks available 165nxt_state = 0 166for bank in range(1, nbr_banks + 1): 167 for stride_size in range(burst_size, max_stride + 1, burst_size): 168 cfg_file.write("STATE %d %d %s %d 0 %d %d " 169 "%d %d %d %d %d %d %d %d %d\n" % 170 (nxt_state, period, options.mode, options.rd_perc, 171 max_addr, burst_size, itt, itt, 0, stride_size, 172 page_size, nbr_banks, bank, options.addr_map, 173 options.mem_ranks)) 174 nxt_state = nxt_state + 1 175 176cfg_file.write("INIT 0\n") 177 178# go through the states one by one 179for state in range(1, nxt_state): 180 cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 181 182cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 183 184cfg_file.close() 185 186# create a traffic generator, and point it to the file we just created 187system.tgen = TrafficGen(config_file = cfg_file_name) 188 189# add a communication monitor 190system.monitor = CommMonitor() 191 192# connect the traffic generator to the bus via a communication monitor 193system.tgen.port = system.monitor.slave 194system.monitor.master = system.membus.slave 195 196# connect the system port even if it is not used in this example 197system.system_port = system.membus.slave 198 199# every period, dump and reset all stats 200periodicStatDump(period) 201 202# run Forrest, run! 203root = Root(full_system = False, system = system) 204root.system.mem_mode = 'timing' 205 206m5.instantiate() 207m5.simulate(nxt_state * period) 208 209print("DRAM sweep with burst: %d, banks: %d, max stride: %d" % 210 (burst_size, nbr_banks, max_stride)) 211