| /gem5/configs/common/ |
| H A D | Caches.py | 57 response_latency = 2 variable in class:L1Cache
73 response_latency = 20 variable in class:L2Cache
82 response_latency = 50 variable in class:IOCache
91 response_latency = 2 variable in class:PageTableWalkerCache
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| H A D | HMC.py | 310 system.membus.response_latency = 2
408 response_latency=opt.xbar_response_latency) for i in
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| /gem5/src/mem/qos/ |
| H A D | QoSMemSinkCtrl.py | 61 response_latency = Param.Latency("20ns", "Memory response latency") variable in class:QoSMemSinkCtrl
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| H A D | mem_sink.cc | 49 responseLatency(p->response_latency),
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| /gem5/src/mem/ |
| H A D | XBar.py | 72 response_latency = Param.Cycles("Response latency") variable in class:BaseXBar
145 response_latency = 1 variable in class:L2XBar
169 response_latency = 2 variable in class:SystemXBar
199 response_latency = 2 variable in class:IOXBar
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| H A D | noncoherent_xbar.cc | 266 Tick response_latency = backdoor ? local
281 pkt->payloadDelay = response_latency;
282 return response_latency;
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| H A D | coherent_xbar.cc | 783 Tick response_latency = 0; local
805 response_latency = backdoor ?
832 response_latency = snoop_response_latency;
871 pkt->payloadDelay = response_latency;
872 return response_latency;
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| H A D | xbar.cc | 62 responseLatency(p->response_latency),
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| /gem5/configs/common/cores/arm/ |
| H A D | ex5_LITTLE.py | 104 response_latency = 2 variable in class:L1Cache
127 response_latency = 2 variable in class:WalkCache
141 response_latency = 9 variable in class:L2
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| H A D | O3_ARM_v7a.py | 155 response_latency = 1 variable in class:O3_ARM_v7a_ICache
168 response_latency = 2 variable in class:O3_ARM_v7a_DCache
182 response_latency = 4 variable in class:O3_ARM_v7aWalkCache
196 response_latency = 12 variable in class:O3_ARM_v7aL2
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| H A D | ex5_big.py | 155 response_latency = 2 variable in class:L1Cache
179 response_latency = 4 variable in class:WalkCache
193 response_latency = 15 variable in class:L2
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| H A D | HPI.py | 1346 response_latency = 4 variable in class:HPI_WalkCache
1369 response_latency = 1 variable in class:HPI_ICache
1379 response_latency = 1 variable in class:HPI_DCache
1392 response_latency = 5 variable in class:HPI_L2
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| /gem5/configs/learning_gem5/part1/ |
| H A D | caches.py | 57 response_latency = 2 variable in class:L1Cache
120 response_latency = 20 variable in class:L2Cache
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| /gem5/configs/example/ |
| H A D | memtest.py | 184 tag_latency = 1, data_latency = 1, response_latency = 1,
204 next.response_latency = prev.response_latency * 10
312 response_latency = 20, tgts_per_mshr = 8,
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| H A D | memcheck.py | 170 tag_latency = 1, data_latency = 1, response_latency = 1,
194 next.response_latency = prev.response_latency * 10
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| H A D | apu_se.py | 445 system.piobus = IOXBar(width=32, response_latency=0,
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| /gem5/configs/example/arm/ |
| H A D | devices.py | 55 response_latency = 1 variable in class:L1I
65 response_latency = 1 variable in class:L1D
76 response_latency = 4 variable in class:WalkCache
87 response_latency = 5 variable in class:L2
101 response_latency = 20 variable in class:L3
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| /gem5/tests/gem5/cpu_tests/ |
| H A D | run.py | 42 response_latency = 1 variable in class:L1Cache
83 response_latency = 1 variable in class:L2Cache
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| /gem5/src/mem/cache/ |
| H A D | Cache.py | 85 response_latency = Param.Cycles("Latency for the return path on a miss"); variable in class:BaseCache
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| /gem5/configs/dram/ |
| H A D | lat_mem_rd.py | 273 response_latency = 40 variable in class:L3Cache
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| /gem5/tests/configs/ |
| H A D | base_config.py | 288 response_latency = 20,
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| H A D | gpu-ruby.py | 281 system.piobus = IOXBar(width=32, response_latency=0,
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| /gem5/configs/ruby/ |
| H A D | MOESI_AMD_Base.py | 174 self.response_latency = 30
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| H A D | GPU_VIPER_Region.py | 295 self.response_latency = 25
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| H A D | GPU_VIPER_Baseline.py | 306 self.response_latency = 30
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