112097Sandreas.sandberg@arm.com# Copyright (c) 2012 The Regents of The University of Michigan 212097Sandreas.sandberg@arm.com# All rights reserved. 312097Sandreas.sandberg@arm.com# 412097Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 512097Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are 612097Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright 712097Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer; 812097Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright 912097Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 1012097Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution; 1112097Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its 1212097Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from 1312097Sandreas.sandberg@arm.com# this software without specific prior written permission. 1412097Sandreas.sandberg@arm.com# 1512097Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1612097Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1712097Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1812097Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1912097Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2012097Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2112097Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2212097Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2312097Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2412097Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2512097Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2612097Sandreas.sandberg@arm.com# 2712097Sandreas.sandberg@arm.com# Authors: Ron Dreslinski 2812097Sandreas.sandberg@arm.com 2913774Sandreas.sandberg@arm.comfrom __future__ import print_function 3013774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 3112097Sandreas.sandberg@arm.com 3212097Sandreas.sandberg@arm.comfrom m5.objects import * 3312097Sandreas.sandberg@arm.com 3412097Sandreas.sandberg@arm.com# Simple ALU Instructions have a latency of 1 3512097Sandreas.sandberg@arm.comclass O3_ARM_v7a_Simple_Int(FUDesc): 3612097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IntAlu', opLat=1) ] 3712097Sandreas.sandberg@arm.com count = 2 3812097Sandreas.sandberg@arm.com 3912097Sandreas.sandberg@arm.com# Complex ALU instructions have a variable latencies 4012097Sandreas.sandberg@arm.comclass O3_ARM_v7a_Complex_Int(FUDesc): 4112097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True), 4212097Sandreas.sandberg@arm.com OpDesc(opClass='IntDiv', opLat=12, pipelined=False), 4312097Sandreas.sandberg@arm.com OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ] 4412097Sandreas.sandberg@arm.com count = 1 4512097Sandreas.sandberg@arm.com 4612097Sandreas.sandberg@arm.com 4712097Sandreas.sandberg@arm.com# Floating point and SIMD instructions 4812097Sandreas.sandberg@arm.comclass O3_ARM_v7a_FP(FUDesc): 4912097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='SimdAdd', opLat=4), 5012097Sandreas.sandberg@arm.com OpDesc(opClass='SimdAddAcc', opLat=4), 5112097Sandreas.sandberg@arm.com OpDesc(opClass='SimdAlu', opLat=4), 5212097Sandreas.sandberg@arm.com OpDesc(opClass='SimdCmp', opLat=4), 5312097Sandreas.sandberg@arm.com OpDesc(opClass='SimdCvt', opLat=3), 5412097Sandreas.sandberg@arm.com OpDesc(opClass='SimdMisc', opLat=3), 5512097Sandreas.sandberg@arm.com OpDesc(opClass='SimdMult',opLat=5), 5612097Sandreas.sandberg@arm.com OpDesc(opClass='SimdMultAcc',opLat=5), 5712097Sandreas.sandberg@arm.com OpDesc(opClass='SimdShift',opLat=3), 5812097Sandreas.sandberg@arm.com OpDesc(opClass='SimdShiftAcc', opLat=3), 5912097Sandreas.sandberg@arm.com OpDesc(opClass='SimdSqrt', opLat=9), 6012097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatAdd',opLat=5), 6112097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatAlu',opLat=5), 6212097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatCmp', opLat=3), 6312097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatCvt', opLat=3), 6412097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatDiv', opLat=3), 6512097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatMisc', opLat=3), 6612097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatMult', opLat=3), 6712097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatMultAcc',opLat=5), 6812097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatSqrt', opLat=9), 6912097Sandreas.sandberg@arm.com OpDesc(opClass='FloatAdd', opLat=5), 7012097Sandreas.sandberg@arm.com OpDesc(opClass='FloatCmp', opLat=5), 7112097Sandreas.sandberg@arm.com OpDesc(opClass='FloatCvt', opLat=5), 7212097Sandreas.sandberg@arm.com OpDesc(opClass='FloatDiv', opLat=9, pipelined=False), 7312097Sandreas.sandberg@arm.com OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False), 7412097Sandreas.sandberg@arm.com OpDesc(opClass='FloatMult', opLat=4), 7512097Sandreas.sandberg@arm.com OpDesc(opClass='FloatMultAcc', opLat=5), 7612097Sandreas.sandberg@arm.com OpDesc(opClass='FloatMisc', opLat=3) ] 7712097Sandreas.sandberg@arm.com count = 2 7812097Sandreas.sandberg@arm.com 7912097Sandreas.sandberg@arm.com 8012097Sandreas.sandberg@arm.com# Load/Store Units 8112097Sandreas.sandberg@arm.comclass O3_ARM_v7a_Load(FUDesc): 8212097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='MemRead',opLat=2), 8312097Sandreas.sandberg@arm.com OpDesc(opClass='FloatMemRead',opLat=2) ] 8412097Sandreas.sandberg@arm.com count = 1 8512097Sandreas.sandberg@arm.com 8612097Sandreas.sandberg@arm.comclass O3_ARM_v7a_Store(FUDesc): 8712097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='MemWrite',opLat=2), 8812097Sandreas.sandberg@arm.com OpDesc(opClass='FloatMemWrite',opLat=2) ] 8912097Sandreas.sandberg@arm.com count = 1 9012097Sandreas.sandberg@arm.com 9112097Sandreas.sandberg@arm.com# Functional Units for this CPU 9212097Sandreas.sandberg@arm.comclass O3_ARM_v7a_FUP(FUPool): 9312097Sandreas.sandberg@arm.com FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(), 9412097Sandreas.sandberg@arm.com O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()] 9512097Sandreas.sandberg@arm.com 9612097Sandreas.sandberg@arm.com# Bi-Mode Branch Predictor 9712097Sandreas.sandberg@arm.comclass O3_ARM_v7a_BP(BiModeBP): 9812097Sandreas.sandberg@arm.com globalPredictorSize = 8192 9912097Sandreas.sandberg@arm.com globalCtrBits = 2 10012097Sandreas.sandberg@arm.com choicePredictorSize = 8192 10112097Sandreas.sandberg@arm.com choiceCtrBits = 2 10212097Sandreas.sandberg@arm.com BTBEntries = 2048 10312097Sandreas.sandberg@arm.com BTBTagSize = 18 10412097Sandreas.sandberg@arm.com RASSize = 16 10512097Sandreas.sandberg@arm.com instShiftAmt = 2 10612097Sandreas.sandberg@arm.com 10712097Sandreas.sandberg@arm.comclass O3_ARM_v7a_3(DerivO3CPU): 10812097Sandreas.sandberg@arm.com LQEntries = 16 10912097Sandreas.sandberg@arm.com SQEntries = 16 11012097Sandreas.sandberg@arm.com LSQDepCheckShift = 0 11112097Sandreas.sandberg@arm.com LFSTSize = 1024 11212097Sandreas.sandberg@arm.com SSITSize = 1024 11312097Sandreas.sandberg@arm.com decodeToFetchDelay = 1 11412097Sandreas.sandberg@arm.com renameToFetchDelay = 1 11512097Sandreas.sandberg@arm.com iewToFetchDelay = 1 11612097Sandreas.sandberg@arm.com commitToFetchDelay = 1 11712097Sandreas.sandberg@arm.com renameToDecodeDelay = 1 11812097Sandreas.sandberg@arm.com iewToDecodeDelay = 1 11912097Sandreas.sandberg@arm.com commitToDecodeDelay = 1 12012097Sandreas.sandberg@arm.com iewToRenameDelay = 1 12112097Sandreas.sandberg@arm.com commitToRenameDelay = 1 12212097Sandreas.sandberg@arm.com commitToIEWDelay = 1 12312097Sandreas.sandberg@arm.com fetchWidth = 3 12412097Sandreas.sandberg@arm.com fetchBufferSize = 16 12512097Sandreas.sandberg@arm.com fetchToDecodeDelay = 3 12612097Sandreas.sandberg@arm.com decodeWidth = 3 12712097Sandreas.sandberg@arm.com decodeToRenameDelay = 2 12812097Sandreas.sandberg@arm.com renameWidth = 3 12912097Sandreas.sandberg@arm.com renameToIEWDelay = 1 13012097Sandreas.sandberg@arm.com issueToExecuteDelay = 1 13112097Sandreas.sandberg@arm.com dispatchWidth = 6 13212097Sandreas.sandberg@arm.com issueWidth = 8 13312097Sandreas.sandberg@arm.com wbWidth = 8 13412097Sandreas.sandberg@arm.com fuPool = O3_ARM_v7a_FUP() 13512097Sandreas.sandberg@arm.com iewToCommitDelay = 1 13612097Sandreas.sandberg@arm.com renameToROBDelay = 1 13712097Sandreas.sandberg@arm.com commitWidth = 8 13812097Sandreas.sandberg@arm.com squashWidth = 8 13912097Sandreas.sandberg@arm.com trapLatency = 13 14012097Sandreas.sandberg@arm.com backComSize = 5 14112097Sandreas.sandberg@arm.com forwardComSize = 5 14212097Sandreas.sandberg@arm.com numPhysIntRegs = 128 14312097Sandreas.sandberg@arm.com numPhysFloatRegs = 192 14412109SRekai.GonzalezAlberquilla@arm.com numPhysVecRegs = 48 14512097Sandreas.sandberg@arm.com numIQEntries = 32 14612097Sandreas.sandberg@arm.com numROBEntries = 40 14712097Sandreas.sandberg@arm.com 14812097Sandreas.sandberg@arm.com switched_out = False 14912097Sandreas.sandberg@arm.com branchPred = O3_ARM_v7a_BP() 15012097Sandreas.sandberg@arm.com 15112097Sandreas.sandberg@arm.com# Instruction Cache 15212097Sandreas.sandberg@arm.comclass O3_ARM_v7a_ICache(Cache): 15312097Sandreas.sandberg@arm.com tag_latency = 1 15412097Sandreas.sandberg@arm.com data_latency = 1 15512097Sandreas.sandberg@arm.com response_latency = 1 15612097Sandreas.sandberg@arm.com mshrs = 2 15712097Sandreas.sandberg@arm.com tgts_per_mshr = 8 15812097Sandreas.sandberg@arm.com size = '32kB' 15912097Sandreas.sandberg@arm.com assoc = 2 16012097Sandreas.sandberg@arm.com is_read_only = True 16112097Sandreas.sandberg@arm.com # Writeback clean lines as well 16212097Sandreas.sandberg@arm.com writeback_clean = True 16312097Sandreas.sandberg@arm.com 16412097Sandreas.sandberg@arm.com# Data Cache 16512097Sandreas.sandberg@arm.comclass O3_ARM_v7a_DCache(Cache): 16612097Sandreas.sandberg@arm.com tag_latency = 2 16712097Sandreas.sandberg@arm.com data_latency = 2 16812097Sandreas.sandberg@arm.com response_latency = 2 16912097Sandreas.sandberg@arm.com mshrs = 6 17012097Sandreas.sandberg@arm.com tgts_per_mshr = 8 17112097Sandreas.sandberg@arm.com size = '32kB' 17212097Sandreas.sandberg@arm.com assoc = 2 17312097Sandreas.sandberg@arm.com write_buffers = 16 17412097Sandreas.sandberg@arm.com # Consider the L2 a victim cache also for clean lines 17512097Sandreas.sandberg@arm.com writeback_clean = True 17612097Sandreas.sandberg@arm.com 17712097Sandreas.sandberg@arm.com# TLB Cache 17812097Sandreas.sandberg@arm.com# Use a cache as a L2 TLB 17912097Sandreas.sandberg@arm.comclass O3_ARM_v7aWalkCache(Cache): 18012097Sandreas.sandberg@arm.com tag_latency = 4 18112097Sandreas.sandberg@arm.com data_latency = 4 18212097Sandreas.sandberg@arm.com response_latency = 4 18312097Sandreas.sandberg@arm.com mshrs = 6 18412097Sandreas.sandberg@arm.com tgts_per_mshr = 8 18512097Sandreas.sandberg@arm.com size = '1kB' 18612097Sandreas.sandberg@arm.com assoc = 8 18712097Sandreas.sandberg@arm.com write_buffers = 16 18812097Sandreas.sandberg@arm.com is_read_only = True 18912097Sandreas.sandberg@arm.com # Writeback clean lines as well 19012097Sandreas.sandberg@arm.com writeback_clean = True 19112097Sandreas.sandberg@arm.com 19212097Sandreas.sandberg@arm.com# L2 Cache 19312097Sandreas.sandberg@arm.comclass O3_ARM_v7aL2(Cache): 19412097Sandreas.sandberg@arm.com tag_latency = 12 19512097Sandreas.sandberg@arm.com data_latency = 12 19612097Sandreas.sandberg@arm.com response_latency = 12 19712097Sandreas.sandberg@arm.com mshrs = 16 19812097Sandreas.sandberg@arm.com tgts_per_mshr = 8 19912097Sandreas.sandberg@arm.com size = '1MB' 20012097Sandreas.sandberg@arm.com assoc = 16 20112097Sandreas.sandberg@arm.com write_buffers = 8 20212097Sandreas.sandberg@arm.com prefetch_on_access = True 20312097Sandreas.sandberg@arm.com clusivity = 'mostly_excl' 20412097Sandreas.sandberg@arm.com # Simple stride prefetcher 20512097Sandreas.sandberg@arm.com prefetcher = StridePrefetcher(degree=8, latency = 1) 20612600Sodanrc@yahoo.com.br tags = BaseSetAssoc() 20714216Sodanrc@yahoo.com.br replacement_policy = RandomRP() 208