1# Copyright (c) 2012 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29from __future__ import print_function
30from __future__ import absolute_import
31
32from m5.objects import *
33
34# Simple ALU Instructions have a latency of 1
35class O3_ARM_v7a_Simple_Int(FUDesc):
36    opList = [ OpDesc(opClass='IntAlu', opLat=1) ]
37    count = 2
38
39# Complex ALU instructions have a variable latencies
40class O3_ARM_v7a_Complex_Int(FUDesc):
41    opList = [ OpDesc(opClass='IntMult', opLat=3, pipelined=True),
42               OpDesc(opClass='IntDiv', opLat=12, pipelined=False),
43               OpDesc(opClass='IprAccess', opLat=3, pipelined=True) ]
44    count = 1
45
46
47# Floating point and SIMD instructions
48class O3_ARM_v7a_FP(FUDesc):
49    opList = [ OpDesc(opClass='SimdAdd', opLat=4),
50               OpDesc(opClass='SimdAddAcc', opLat=4),
51               OpDesc(opClass='SimdAlu', opLat=4),
52               OpDesc(opClass='SimdCmp', opLat=4),
53               OpDesc(opClass='SimdCvt', opLat=3),
54               OpDesc(opClass='SimdMisc', opLat=3),
55               OpDesc(opClass='SimdMult',opLat=5),
56               OpDesc(opClass='SimdMultAcc',opLat=5),
57               OpDesc(opClass='SimdShift',opLat=3),
58               OpDesc(opClass='SimdShiftAcc', opLat=3),
59               OpDesc(opClass='SimdSqrt', opLat=9),
60               OpDesc(opClass='SimdFloatAdd',opLat=5),
61               OpDesc(opClass='SimdFloatAlu',opLat=5),
62               OpDesc(opClass='SimdFloatCmp', opLat=3),
63               OpDesc(opClass='SimdFloatCvt', opLat=3),
64               OpDesc(opClass='SimdFloatDiv', opLat=3),
65               OpDesc(opClass='SimdFloatMisc', opLat=3),
66               OpDesc(opClass='SimdFloatMult', opLat=3),
67               OpDesc(opClass='SimdFloatMultAcc',opLat=5),
68               OpDesc(opClass='SimdFloatSqrt', opLat=9),
69               OpDesc(opClass='FloatAdd', opLat=5),
70               OpDesc(opClass='FloatCmp', opLat=5),
71               OpDesc(opClass='FloatCvt', opLat=5),
72               OpDesc(opClass='FloatDiv', opLat=9, pipelined=False),
73               OpDesc(opClass='FloatSqrt', opLat=33, pipelined=False),
74               OpDesc(opClass='FloatMult', opLat=4),
75               OpDesc(opClass='FloatMultAcc', opLat=5),
76               OpDesc(opClass='FloatMisc', opLat=3) ]
77    count = 2
78
79
80# Load/Store Units
81class O3_ARM_v7a_Load(FUDesc):
82    opList = [ OpDesc(opClass='MemRead',opLat=2),
83               OpDesc(opClass='FloatMemRead',opLat=2) ]
84    count = 1
85
86class O3_ARM_v7a_Store(FUDesc):
87    opList = [ OpDesc(opClass='MemWrite',opLat=2),
88               OpDesc(opClass='FloatMemWrite',opLat=2) ]
89    count = 1
90
91# Functional Units for this CPU
92class O3_ARM_v7a_FUP(FUPool):
93    FUList = [O3_ARM_v7a_Simple_Int(), O3_ARM_v7a_Complex_Int(),
94              O3_ARM_v7a_Load(), O3_ARM_v7a_Store(), O3_ARM_v7a_FP()]
95
96# Bi-Mode Branch Predictor
97class O3_ARM_v7a_BP(BiModeBP):
98    globalPredictorSize = 8192
99    globalCtrBits = 2
100    choicePredictorSize = 8192
101    choiceCtrBits = 2
102    BTBEntries = 2048
103    BTBTagSize = 18
104    RASSize = 16
105    instShiftAmt = 2
106
107class O3_ARM_v7a_3(DerivO3CPU):
108    LQEntries = 16
109    SQEntries = 16
110    LSQDepCheckShift = 0
111    LFSTSize = 1024
112    SSITSize = 1024
113    decodeToFetchDelay = 1
114    renameToFetchDelay = 1
115    iewToFetchDelay = 1
116    commitToFetchDelay = 1
117    renameToDecodeDelay = 1
118    iewToDecodeDelay = 1
119    commitToDecodeDelay = 1
120    iewToRenameDelay = 1
121    commitToRenameDelay = 1
122    commitToIEWDelay = 1
123    fetchWidth = 3
124    fetchBufferSize = 16
125    fetchToDecodeDelay = 3
126    decodeWidth = 3
127    decodeToRenameDelay = 2
128    renameWidth = 3
129    renameToIEWDelay = 1
130    issueToExecuteDelay = 1
131    dispatchWidth = 6
132    issueWidth = 8
133    wbWidth = 8
134    fuPool = O3_ARM_v7a_FUP()
135    iewToCommitDelay = 1
136    renameToROBDelay = 1
137    commitWidth = 8
138    squashWidth = 8
139    trapLatency = 13
140    backComSize = 5
141    forwardComSize = 5
142    numPhysIntRegs = 128
143    numPhysFloatRegs = 192
144    numPhysVecRegs = 48
145    numIQEntries = 32
146    numROBEntries = 40
147
148    switched_out = False
149    branchPred = O3_ARM_v7a_BP()
150
151# Instruction Cache
152class O3_ARM_v7a_ICache(Cache):
153    tag_latency = 1
154    data_latency = 1
155    response_latency = 1
156    mshrs = 2
157    tgts_per_mshr = 8
158    size = '32kB'
159    assoc = 2
160    is_read_only = True
161    # Writeback clean lines as well
162    writeback_clean = True
163
164# Data Cache
165class O3_ARM_v7a_DCache(Cache):
166    tag_latency = 2
167    data_latency = 2
168    response_latency = 2
169    mshrs = 6
170    tgts_per_mshr = 8
171    size = '32kB'
172    assoc = 2
173    write_buffers = 16
174    # Consider the L2 a victim cache also for clean lines
175    writeback_clean = True
176
177# TLB Cache
178# Use a cache as a L2 TLB
179class O3_ARM_v7aWalkCache(Cache):
180    tag_latency = 4
181    data_latency = 4
182    response_latency = 4
183    mshrs = 6
184    tgts_per_mshr = 8
185    size = '1kB'
186    assoc = 8
187    write_buffers = 16
188    is_read_only = True
189    # Writeback clean lines as well
190    writeback_clean = True
191
192# L2 Cache
193class O3_ARM_v7aL2(Cache):
194    tag_latency = 12
195    data_latency = 12
196    response_latency = 12
197    mshrs = 16
198    tgts_per_mshr = 8
199    size = '1MB'
200    assoc = 16
201    write_buffers = 8
202    prefetch_on_access = True
203    clusivity = 'mostly_excl'
204    # Simple stride prefetcher
205    prefetcher = StridePrefetcher(degree=8, latency = 1)
206    tags = BaseSetAssoc()
207    replacement_policy = RandomRP()
208