12497SN/A/*
212780Snikos.nikoleris@arm.com * Copyright (c) 2011-2015, 2018 ARM Limited
38711SN/A * All rights reserved
48711SN/A *
58711SN/A * The license below extends only to copyright in the software and shall
68711SN/A * not be construed as granting a license to any other intellectual
78711SN/A * property including but not limited to intellectual property relating
88711SN/A * to a hardware implementation of the functionality of the software
98711SN/A * licensed hereunder.  You may use the software subject to the license
108711SN/A * terms below provided that you ensure that this notice is replicated
118711SN/A * unmodified and in its entirety in all distributions of the software,
128711SN/A * modified or unmodified, in source code or in binary form.
138711SN/A *
142497SN/A * Copyright (c) 2006 The Regents of The University of Michigan
152497SN/A * All rights reserved.
162497SN/A *
172497SN/A * Redistribution and use in source and binary forms, with or without
182497SN/A * modification, are permitted provided that the following conditions are
192497SN/A * met: redistributions of source code must retain the above copyright
202497SN/A * notice, this list of conditions and the following disclaimer;
212497SN/A * redistributions in binary form must reproduce the above copyright
222497SN/A * notice, this list of conditions and the following disclaimer in the
232497SN/A * documentation and/or other materials provided with the distribution;
242497SN/A * neither the name of the copyright holders nor the names of its
252497SN/A * contributors may be used to endorse or promote products derived from
262497SN/A * this software without specific prior written permission.
272497SN/A *
282497SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
292497SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
302497SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
312497SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
322497SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
332497SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
342497SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
352497SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
362497SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
372497SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
382497SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665SN/A *
402665SN/A * Authors: Ali Saidi
418715SN/A *          Andreas Hansson
428922SN/A *          William Wang
432497SN/A */
442497SN/A
452497SN/A/**
462982SN/A * @file
4710405Sandreas.hansson@arm.com * Definition of a non-coherent crossbar object.
482497SN/A */
492497SN/A
5011793Sbrandon.potter@amd.com#include "mem/noncoherent_xbar.hh"
5111793Sbrandon.potter@amd.com
5212334Sgabeblack@google.com#include "base/logging.hh"
532548SN/A#include "base/trace.hh"
5410405Sandreas.hansson@arm.com#include "debug/NoncoherentXBar.hh"
5510405Sandreas.hansson@arm.com#include "debug/XBar.hh"
562497SN/A
5710405Sandreas.hansson@arm.comNoncoherentXBar::NoncoherentXBar(const NoncoherentXBarParams *p)
5810405Sandreas.hansson@arm.com    : BaseXBar(p)
597523SN/A{
608851SN/A    // create the ports based on the size of the master and slave
618948SN/A    // vector ports, and the presence of the default port, the ports
628948SN/A    // are enumerated starting from zero
638851SN/A    for (int i = 0; i < p->port_master_connection_count; ++i) {
649095SN/A        std::string portName = csprintf("%s.master[%d]", name(), i);
6510405Sandreas.hansson@arm.com        MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this, i);
668922SN/A        masterPorts.push_back(bp);
679715SN/A        reqLayers.push_back(new ReqLayer(*bp, *this,
689715SN/A                                         csprintf(".reqLayer%d", i)));
698851SN/A    }
708851SN/A
718948SN/A    // see if we have a default slave device connected and if so add
728948SN/A    // our corresponding master port
738915SN/A    if (p->port_default_connection_count) {
749031SN/A        defaultPortID = masterPorts.size();
759095SN/A        std::string portName = name() + ".default";
7610405Sandreas.hansson@arm.com        MasterPort* bp = new NoncoherentXBarMasterPort(portName, *this,
779036SN/A                                                      defaultPortID);
788922SN/A        masterPorts.push_back(bp);
799715SN/A        reqLayers.push_back(new ReqLayer(*bp, *this, csprintf(".reqLayer%d",
809715SN/A                                                              defaultPortID)));
818915SN/A    }
828915SN/A
838948SN/A    // create the slave ports, once again starting at zero
848851SN/A    for (int i = 0; i < p->port_slave_connection_count; ++i) {
859095SN/A        std::string portName = csprintf("%s.slave[%d]", name(), i);
8610888Sandreas.hansson@arm.com        QueuedSlavePort* bp = new NoncoherentXBarSlavePort(portName, *this, i);
878922SN/A        slavePorts.push_back(bp);
889715SN/A        respLayers.push_back(new RespLayer(*bp, *this,
899715SN/A                                           csprintf(".respLayer%d", i)));
908851SN/A    }
917523SN/A}
927523SN/A
9310405Sandreas.hansson@arm.comNoncoherentXBar::~NoncoherentXBar()
949715SN/A{
9510405Sandreas.hansson@arm.com    for (auto l: reqLayers)
9610405Sandreas.hansson@arm.com        delete l;
9710405Sandreas.hansson@arm.com    for (auto l: respLayers)
9810405Sandreas.hansson@arm.com        delete l;
999715SN/A}
1009715SN/A
1018948SN/Abool
10210405Sandreas.hansson@arm.comNoncoherentXBar::recvTimingReq(PacketPtr pkt, PortID slave_port_id)
1033244SN/A{
1048975SN/A    // determine the source port based on the id
1059032SN/A    SlavePort *src_port = slavePorts[slave_port_id];
1063244SN/A
10710405Sandreas.hansson@arm.com    // we should never see express snoops on a non-coherent crossbar
1089036SN/A    assert(!pkt->isExpressSnoop());
1099036SN/A
1109612SN/A    // determine the destination based on the address
11113856Sodanrc@yahoo.com.br    PortID master_port_id = findPort(pkt->getAddrRange());
1129612SN/A
11310405Sandreas.hansson@arm.com    // test if the layer should be considered occupied for the current
1149036SN/A    // port
1159715SN/A    if (!reqLayers[master_port_id]->tryTiming(src_port)) {
11610405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x BUSY\n",
1178949SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1183244SN/A        return false;
1193244SN/A    }
1203244SN/A
12110405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x\n",
1228949SN/A            src_port->name(), pkt->cmdString(), pkt->getAddr());
1235197SN/A
1249712SN/A    // store size and command as they might be modified when
1259712SN/A    // forwarding the packet
1269712SN/A    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
1279712SN/A    unsigned int pkt_cmd = pkt->cmdToIndex();
1289712SN/A
12910719SMarco.Balboni@ARM.com    // store the old header delay so we can restore it if needed
13010719SMarco.Balboni@ARM.com    Tick old_header_delay = pkt->headerDelay;
13110719SMarco.Balboni@ARM.com
13210719SMarco.Balboni@ARM.com    // a request sees the frontend and forward latency
13310719SMarco.Balboni@ARM.com    Tick xbar_delay = (frontendLatency + forwardLatency) * clockPeriod();
13410719SMarco.Balboni@ARM.com
13510719SMarco.Balboni@ARM.com    // set the packet header and payload delay
13610719SMarco.Balboni@ARM.com    calcPacketTiming(pkt, xbar_delay);
13710719SMarco.Balboni@ARM.com
13810719SMarco.Balboni@ARM.com    // determine how long to be crossbar layer is busy
13910719SMarco.Balboni@ARM.com    Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
1408915SN/A
14110656Sandreas.hansson@arm.com    // before forwarding the packet (and possibly altering it),
14210656Sandreas.hansson@arm.com    // remember if we are expecting a response
14310656Sandreas.hansson@arm.com    const bool expect_response = pkt->needsResponse() &&
14411284Sandreas.hansson@arm.com        !pkt->cacheResponding();
14510656Sandreas.hansson@arm.com
1469612SN/A    // since it is a normal request, attempt to send the packet
1479712SN/A    bool success = masterPorts[master_port_id]->sendTimingReq(pkt);
1488948SN/A
1498975SN/A    if (!success)  {
15010405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingReq: src %s %s 0x%x RETRY\n",
1518975SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1528948SN/A
15310719SMarco.Balboni@ARM.com        // restore the header delay as it is additive
15410719SMarco.Balboni@ARM.com        pkt->headerDelay = old_header_delay;
1559549SN/A
1569547SN/A        // occupy until the header is sent
1579715SN/A        reqLayers[master_port_id]->failedTiming(src_port,
15810719SMarco.Balboni@ARM.com                                                clockEdge(Cycles(1)));
1598948SN/A
1608975SN/A        return false;
1618975SN/A    }
1628975SN/A
16310656Sandreas.hansson@arm.com    // remember where to route the response to
16410656Sandreas.hansson@arm.com    if (expect_response) {
16510656Sandreas.hansson@arm.com        assert(routeTo.find(pkt->req) == routeTo.end());
16610656Sandreas.hansson@arm.com        routeTo[pkt->req] = slave_port_id;
16710656Sandreas.hansson@arm.com    }
16810656Sandreas.hansson@arm.com
1699715SN/A    reqLayers[master_port_id]->succeededTiming(packetFinishTime);
1708975SN/A
1719712SN/A    // stats updates
1729712SN/A    pktCount[slave_port_id][master_port_id]++;
17310405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
1749712SN/A    transDist[pkt_cmd]++;
1759712SN/A
1768975SN/A    return true;
1778975SN/A}
1788975SN/A
1798975SN/Abool
18010405Sandreas.hansson@arm.comNoncoherentXBar::recvTimingResp(PacketPtr pkt, PortID master_port_id)
1818975SN/A{
1828975SN/A    // determine the source port based on the id
1839032SN/A    MasterPort *src_port = masterPorts[master_port_id];
1848975SN/A
18510656Sandreas.hansson@arm.com    // determine the destination
18610656Sandreas.hansson@arm.com    const auto route_lookup = routeTo.find(pkt->req);
18710656Sandreas.hansson@arm.com    assert(route_lookup != routeTo.end());
18810656Sandreas.hansson@arm.com    const PortID slave_port_id = route_lookup->second;
18910572Sandreas.hansson@arm.com    assert(slave_port_id != InvalidPortID);
19010572Sandreas.hansson@arm.com    assert(slave_port_id < respLayers.size());
1919713SN/A
19210405Sandreas.hansson@arm.com    // test if the layer should be considered occupied for the current
1939033SN/A    // port
1949715SN/A    if (!respLayers[slave_port_id]->tryTiming(src_port)) {
19510405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x BUSY\n",
1968975SN/A                src_port->name(), pkt->cmdString(), pkt->getAddr());
1978975SN/A        return false;
1988975SN/A    }
1998975SN/A
20010405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvTimingResp: src %s %s 0x%x\n",
2018975SN/A            src_port->name(), pkt->cmdString(), pkt->getAddr());
2028975SN/A
2039712SN/A    // store size and command as they might be modified when
2049712SN/A    // forwarding the packet
2059712SN/A    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
2069712SN/A    unsigned int pkt_cmd = pkt->cmdToIndex();
2079712SN/A
20810719SMarco.Balboni@ARM.com    // a response sees the response latency
20910719SMarco.Balboni@ARM.com    Tick xbar_delay = responseLatency * clockPeriod();
21010719SMarco.Balboni@ARM.com
21110719SMarco.Balboni@ARM.com    // set the packet header and payload delay
21210719SMarco.Balboni@ARM.com    calcPacketTiming(pkt, xbar_delay);
21310719SMarco.Balboni@ARM.com
21410719SMarco.Balboni@ARM.com    // determine how long to be crossbar layer is busy
21510719SMarco.Balboni@ARM.com    Tick packetFinishTime = clockEdge(Cycles(1)) + pkt->payloadDelay;
2168975SN/A
21710888Sandreas.hansson@arm.com    // send the packet through the destination slave port, and pay for
21810888Sandreas.hansson@arm.com    // any outstanding latency
21910888Sandreas.hansson@arm.com    Tick latency = pkt->headerDelay;
22010888Sandreas.hansson@arm.com    pkt->headerDelay = 0;
22110888Sandreas.hansson@arm.com    slavePorts[slave_port_id]->schedTimingResp(pkt, curTick() + latency);
2228975SN/A
22310656Sandreas.hansson@arm.com    // remove the request from the routing table
22410656Sandreas.hansson@arm.com    routeTo.erase(route_lookup);
22510656Sandreas.hansson@arm.com
2269715SN/A    respLayers[slave_port_id]->succeededTiming(packetFinishTime);
2278975SN/A
2289712SN/A    // stats updates
2299712SN/A    pktCount[slave_port_id][master_port_id]++;
23010405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
2319712SN/A    transDist[pkt_cmd]++;
2329712SN/A
2338975SN/A    return true;
2348975SN/A}
2358975SN/A
2369092SN/Avoid
23710713Sandreas.hansson@arm.comNoncoherentXBar::recvReqRetry(PortID master_port_id)
2389092SN/A{
2399093SN/A    // responses never block on forwarding them, so the retry will
2409093SN/A    // always be coming from a port to which we tried to forward a
2419093SN/A    // request
2429715SN/A    reqLayers[master_port_id]->recvRetry();
2439092SN/A}
2449092SN/A
2459036SN/ATick
24613847Sgabeblack@google.comNoncoherentXBar::recvAtomicBackdoor(PacketPtr pkt, PortID slave_port_id,
24713847Sgabeblack@google.com                                    MemBackdoorPtr *backdoor)
2488975SN/A{
24910405Sandreas.hansson@arm.com    DPRINTF(NoncoherentXBar, "recvAtomic: packet src %s addr 0x%x cmd %s\n",
2509032SN/A            slavePorts[slave_port_id]->name(), pkt->getAddr(),
2518949SN/A            pkt->cmdString());
2528915SN/A
25310405Sandreas.hansson@arm.com    unsigned int pkt_size = pkt->hasData() ? pkt->getSize() : 0;
25410405Sandreas.hansson@arm.com    unsigned int pkt_cmd = pkt->cmdToIndex();
2559712SN/A
2569036SN/A    // determine the destination port
25713856Sodanrc@yahoo.com.br    PortID master_port_id = findPort(pkt->getAddrRange());
25810405Sandreas.hansson@arm.com
25910405Sandreas.hansson@arm.com    // stats updates for the request
26010405Sandreas.hansson@arm.com    pktCount[slave_port_id][master_port_id]++;
26110405Sandreas.hansson@arm.com    pktSize[slave_port_id][master_port_id] += pkt_size;
26210405Sandreas.hansson@arm.com    transDist[pkt_cmd]++;
2638948SN/A
2648948SN/A    // forward the request to the appropriate destination
26513847Sgabeblack@google.com    auto master = masterPorts[master_port_id];
26613847Sgabeblack@google.com    Tick response_latency = backdoor ?
26713847Sgabeblack@google.com        master->sendAtomicBackdoor(pkt, *backdoor) : master->sendAtomic(pkt);
2688948SN/A
2699712SN/A    // add the response data
27010405Sandreas.hansson@arm.com    if (pkt->isResponse()) {
27110405Sandreas.hansson@arm.com        pkt_size = pkt->hasData() ? pkt->getSize() : 0;
27210405Sandreas.hansson@arm.com        pkt_cmd = pkt->cmdToIndex();
27310405Sandreas.hansson@arm.com
27410405Sandreas.hansson@arm.com        // stats updates
27510405Sandreas.hansson@arm.com        pktCount[slave_port_id][master_port_id]++;
27610405Sandreas.hansson@arm.com        pktSize[slave_port_id][master_port_id] += pkt_size;
27710405Sandreas.hansson@arm.com        transDist[pkt_cmd]++;
27810405Sandreas.hansson@arm.com    }
2799712SN/A
2809547SN/A    // @todo: Not setting first-word time
28110694SMarco.Balboni@ARM.com    pkt->payloadDelay = response_latency;
2828948SN/A    return response_latency;
2838948SN/A}
2848948SN/A
2852497SN/Avoid
28610405Sandreas.hansson@arm.comNoncoherentXBar::recvFunctional(PacketPtr pkt, PortID slave_port_id)
2872497SN/A{
2888663SN/A    if (!pkt->isPrint()) {
2898663SN/A        // don't do DPRINTFs on PrintReq as it clutters up the output
29010405Sandreas.hansson@arm.com        DPRINTF(NoncoherentXBar,
2918949SN/A                "recvFunctional: packet src %s addr 0x%x cmd %s\n",
2929032SN/A                slavePorts[slave_port_id]->name(), pkt->getAddr(),
2938663SN/A                pkt->cmdString());
2948663SN/A    }
2958663SN/A
29610888Sandreas.hansson@arm.com    // since our slave ports are queued ports we need to check them as well
29710888Sandreas.hansson@arm.com    for (const auto& p : slavePorts) {
29810888Sandreas.hansson@arm.com        // if we find a response that has the data, then the
29910888Sandreas.hansson@arm.com        // downstream caches/memories may be out of date, so simply stop
30010888Sandreas.hansson@arm.com        // here
30112823Srmk35@cl.cam.ac.uk        if (p->trySatisfyFunctional(pkt)) {
30210888Sandreas.hansson@arm.com            if (pkt->needsResponse())
30310888Sandreas.hansson@arm.com                pkt->makeResponse();
30410888Sandreas.hansson@arm.com            return;
30510888Sandreas.hansson@arm.com        }
30610888Sandreas.hansson@arm.com    }
30710888Sandreas.hansson@arm.com
3089036SN/A    // determine the destination port
30913856Sodanrc@yahoo.com.br    PortID dest_id = findPort(pkt->getAddrRange());
3104912SN/A
3119036SN/A    // forward the request to the appropriate destination
3129036SN/A    masterPorts[dest_id]->sendFunctional(pkt);
3138948SN/A}
3148948SN/A
31510405Sandreas.hansson@arm.comNoncoherentXBar*
31610405Sandreas.hansson@arm.comNoncoherentXBarParams::create()
3178948SN/A{
31810405Sandreas.hansson@arm.com    return new NoncoherentXBar(this);
3198948SN/A}
3209712SN/A
3219712SN/Avoid
32210405Sandreas.hansson@arm.comNoncoherentXBar::regStats()
3239712SN/A{
32410405Sandreas.hansson@arm.com    // register the stats of the base class and our layers
32510405Sandreas.hansson@arm.com    BaseXBar::regStats();
32610405Sandreas.hansson@arm.com    for (auto l: reqLayers)
32710405Sandreas.hansson@arm.com        l->regStats();
32810405Sandreas.hansson@arm.com    for (auto l: respLayers)
32910405Sandreas.hansson@arm.com        l->regStats();
3309712SN/A}
331