114006Stiago.muck@arm.com# Copyright (c) 2012, 2015, 2017, 2019 ARM Limited 29036SN/A# All rights reserved. 39036SN/A# 49036SN/A# The license below extends only to copyright in the software and shall 59036SN/A# not be construed as granting a license to any other intellectual 69036SN/A# property including but not limited to intellectual property relating 79036SN/A# to a hardware implementation of the functionality of the software 89036SN/A# licensed hereunder. You may use the software subject to the license 99036SN/A# terms below provided that you ensure that this notice is replicated 109036SN/A# unmodified and in its entirety in all distributions of the software, 119036SN/A# modified or unmodified, in source code or in binary form. 129036SN/A# 135354SN/A# Copyright (c) 2005-2008 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 394486SN/A# Authors: Nathan Binkert 409036SN/A# Andreas Hansson 414486SN/A 4213665Sandreas.sandberg@arm.comfrom m5.objects.System import System 433102SN/Afrom m5.params import * 449524SN/Afrom m5.proxy import * 4510399SN/Afrom m5.SimObject import SimObject 464486SN/A 4713892Sgabeblack@google.comfrom m5.objects.ClockedObject import ClockedObject 4813665Sandreas.sandberg@arm.com 4913892Sgabeblack@google.comclass BaseXBar(ClockedObject): 5010405Sandreas.hansson@arm.com type = 'BaseXBar' 519036SN/A abstract = True 5210405Sandreas.hansson@arm.com cxx_header = "mem/xbar.hh" 5310719SMarco.Balboni@ARM.com 5410719SMarco.Balboni@ARM.com slave = VectorSlavePort("Vector port for connecting masters") 5510719SMarco.Balboni@ARM.com master = VectorMasterPort("Vector port for connecting slaves") 5610719SMarco.Balboni@ARM.com 5710719SMarco.Balboni@ARM.com # Latencies governing the time taken for the variuos paths a 5810719SMarco.Balboni@ARM.com # packet has through the crossbar. Note that the crossbar itself 5910719SMarco.Balboni@ARM.com # does not add the latency due to assumptions in the coherency 6010719SMarco.Balboni@ARM.com # mechanism. Instead the latency is annotated on the packet and 6110719SMarco.Balboni@ARM.com # left to the neighbouring modules. 6210719SMarco.Balboni@ARM.com # 6310719SMarco.Balboni@ARM.com # A request incurs the frontend latency, possibly snoop filter 6410719SMarco.Balboni@ARM.com # lookup latency, and forward latency. A response incurs the 6510719SMarco.Balboni@ARM.com # response latency. Frontend latency encompasses arbitration and 6610719SMarco.Balboni@ARM.com # deciding what to do when a request arrives. the forward latency 6710719SMarco.Balboni@ARM.com # is the latency involved once a decision is made to forward the 6810719SMarco.Balboni@ARM.com # request. The response latency, is similar to the forward 6910719SMarco.Balboni@ARM.com # latency, but for responses rather than requests. 7010720Sandreas.hansson@arm.com frontend_latency = Param.Cycles("Frontend latency") 7110720Sandreas.hansson@arm.com forward_latency = Param.Cycles("Forward latency") 7210720Sandreas.hansson@arm.com response_latency = Param.Cycles("Response latency") 7310719SMarco.Balboni@ARM.com 7410719SMarco.Balboni@ARM.com # Width governing the throughput of the crossbar 7510720Sandreas.hansson@arm.com width = Param.Unsigned("Datapath width per port (bytes)") 769036SN/A 779036SN/A # The default port can be left unconnected, or be used to connect 789036SN/A # a default slave port 799036SN/A default = MasterPort("Port for connecting an optional default slave") 809036SN/A 819036SN/A # The default port can be used unconditionally, or based on 829036SN/A # address range, in which case it may overlap with other 839036SN/A # ports. The default range is always checked first, thus creating 849036SN/A # a two-level hierarchical lookup. This is useful e.g. for the PCI 8510405Sandreas.hansson@arm.com # xbar configuration. 869036SN/A use_default_range = Param.Bool(False, "Perform address mapping for " \ 879036SN/A "the default port") 889036SN/A 8910405Sandreas.hansson@arm.comclass NoncoherentXBar(BaseXBar): 9010405Sandreas.hansson@arm.com type = 'NoncoherentXBar' 9110405Sandreas.hansson@arm.com cxx_header = "mem/noncoherent_xbar.hh" 929036SN/A 9310405Sandreas.hansson@arm.comclass CoherentXBar(BaseXBar): 9410405Sandreas.hansson@arm.com type = 'CoherentXBar' 9510405Sandreas.hansson@arm.com cxx_header = "mem/coherent_xbar.hh" 969524SN/A 9710719SMarco.Balboni@ARM.com # The coherent crossbar additionally has snoop responses that are 9810719SMarco.Balboni@ARM.com # forwarded after a specific latency. 9910720Sandreas.hansson@arm.com snoop_response_latency = Param.Cycles("Snoop response latency") 10010719SMarco.Balboni@ARM.com 10110719SMarco.Balboni@ARM.com # An optional snoop filter 10210719SMarco.Balboni@ARM.com snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter") 10310719SMarco.Balboni@ARM.com 10414006Stiago.muck@arm.com # Maximum number of outstanding snoop requests for sanity checks 10514006Stiago.muck@arm.com max_outstanding_snoops = Param.Int(512, "Max. outstanding snoops allowed") 10614006Stiago.muck@arm.com 10714006Stiago.muck@arm.com # Maximum routing table size for sanity checks 10814006Stiago.muck@arm.com max_routing_table_size = Param.Int(512, "Max. routing table size") 10914006Stiago.muck@arm.com 11011334Sandreas.hansson@arm.com # Determine how this crossbar handles packets where caches have 11111334Sandreas.hansson@arm.com # already committed to responding, by establishing if the crossbar 11211334Sandreas.hansson@arm.com # is the point of coherency or not. 11311334Sandreas.hansson@arm.com point_of_coherency = Param.Bool(False, "Consider this crossbar the " \ 11411334Sandreas.hansson@arm.com "point of coherency") 11511334Sandreas.hansson@arm.com 11612341Snikos.nikoleris@arm.com # Specify whether this crossbar is the point of unification. 11712341Snikos.nikoleris@arm.com point_of_unification = Param.Bool(False, "Consider this crossbar the " \ 11812341Snikos.nikoleris@arm.com "point of unification") 11912341Snikos.nikoleris@arm.com 12010405Sandreas.hansson@arm.com system = Param.System(Parent.any, "System that the crossbar belongs to.") 12110399SN/A 12210399SN/Aclass SnoopFilter(SimObject): 12310399SN/A type = 'SnoopFilter' 12410399SN/A cxx_header = "mem/snoop_filter.hh" 12510719SMarco.Balboni@ARM.com 12610719SMarco.Balboni@ARM.com # Lookup latency of the snoop filter, added to requests that pass 12710719SMarco.Balboni@ARM.com # through a coherent crossbar. 12810719SMarco.Balboni@ARM.com lookup_latency = Param.Cycles(1, "Lookup latency") 12910399SN/A 13010405Sandreas.hansson@arm.com system = Param.System(Parent.any, "System that the crossbar belongs to.") 13110720Sandreas.hansson@arm.com 13211132Sali.jafri@arm.com # Sanity check on max capacity to track, adjust if needed. 13311132Sali.jafri@arm.com max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter") 13411132Sali.jafri@arm.com 13510720Sandreas.hansson@arm.com# We use a coherent crossbar to connect multiple masters to the L2 13610720Sandreas.hansson@arm.com# caches. Normally this crossbar would be part of the cache itself. 13710720Sandreas.hansson@arm.comclass L2XBar(CoherentXBar): 13810720Sandreas.hansson@arm.com # 256-bit crossbar by default 13910720Sandreas.hansson@arm.com width = 32 14010720Sandreas.hansson@arm.com 14110720Sandreas.hansson@arm.com # Assume that most of this is covered by the cache latencies, with 14210720Sandreas.hansson@arm.com # no more than a single pipeline stage for any packet. 14310720Sandreas.hansson@arm.com frontend_latency = 1 14410720Sandreas.hansson@arm.com forward_latency = 0 14510720Sandreas.hansson@arm.com response_latency = 1 14610720Sandreas.hansson@arm.com snoop_response_latency = 1 14710720Sandreas.hansson@arm.com 14811132Sali.jafri@arm.com # Use a snoop-filter by default, and set the latency to zero as 14911132Sali.jafri@arm.com # the lookup is assumed to overlap with the frontend latency of 15011132Sali.jafri@arm.com # the crossbar 15111132Sali.jafri@arm.com snoop_filter = SnoopFilter(lookup_latency = 0) 15211132Sali.jafri@arm.com 15312341Snikos.nikoleris@arm.com # This specialisation of the coherent crossbar is to be considered 15412341Snikos.nikoleris@arm.com # the point of unification, it connects the dcache and the icache 15512341Snikos.nikoleris@arm.com # to the first level of unified cache. 15612341Snikos.nikoleris@arm.com point_of_unification = True 15712341Snikos.nikoleris@arm.com 15810720Sandreas.hansson@arm.com# One of the key coherent crossbar instances is the system 15910720Sandreas.hansson@arm.com# interconnect, tying together the CPU clusters, GPUs, and any I/O 16010720Sandreas.hansson@arm.com# coherent masters, and DRAM controllers. 16110720Sandreas.hansson@arm.comclass SystemXBar(CoherentXBar): 16210720Sandreas.hansson@arm.com # 128-bit crossbar by default 16310720Sandreas.hansson@arm.com width = 16 16410720Sandreas.hansson@arm.com 16510720Sandreas.hansson@arm.com # A handful pipeline stages for each portion of the latency 16610720Sandreas.hansson@arm.com # contributions. 16710720Sandreas.hansson@arm.com frontend_latency = 3 16810720Sandreas.hansson@arm.com forward_latency = 4 16910720Sandreas.hansson@arm.com response_latency = 2 17010720Sandreas.hansson@arm.com snoop_response_latency = 4 17110720Sandreas.hansson@arm.com 17211604Sandreas.hansson@arm.com # Use a snoop-filter by default 17311604Sandreas.hansson@arm.com snoop_filter = SnoopFilter(lookup_latency = 1) 17411604Sandreas.hansson@arm.com 17511334Sandreas.hansson@arm.com # This specialisation of the coherent crossbar is to be considered 17611334Sandreas.hansson@arm.com # the point of coherency, as there are no (coherent) downstream 17711334Sandreas.hansson@arm.com # caches. 17811334Sandreas.hansson@arm.com point_of_coherency = True 17911334Sandreas.hansson@arm.com 18012341Snikos.nikoleris@arm.com # This specialisation of the coherent crossbar is to be considered 18112341Snikos.nikoleris@arm.com # the point of unification, it connects the dcache and the icache 18212341Snikos.nikoleris@arm.com # to the first level of unified cache. This is needed for systems 18312341Snikos.nikoleris@arm.com # without caches where the SystemXBar is also the point of 18412341Snikos.nikoleris@arm.com # unification. 18512341Snikos.nikoleris@arm.com point_of_unification = True 18612341Snikos.nikoleris@arm.com 18710720Sandreas.hansson@arm.com# In addition to the system interconnect, we typically also have one 18810720Sandreas.hansson@arm.com# or more on-chip I/O crossbars. Note that at some point we might want 18910720Sandreas.hansson@arm.com# to also define an off-chip I/O crossbar such as PCIe. 19010720Sandreas.hansson@arm.comclass IOXBar(NoncoherentXBar): 19110720Sandreas.hansson@arm.com # 128-bit crossbar by default 19210720Sandreas.hansson@arm.com width = 16 19310720Sandreas.hansson@arm.com 19410720Sandreas.hansson@arm.com # Assume a simpler datapath than a coherent crossbar, incuring 19510720Sandreas.hansson@arm.com # less pipeline stages for decision making and forwarding of 19610720Sandreas.hansson@arm.com # requests. 19710720Sandreas.hansson@arm.com frontend_latency = 2 19810720Sandreas.hansson@arm.com forward_latency = 1 19910720Sandreas.hansson@arm.com response_latency = 2 200