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38#
39# Authors: Nathan Binkert
40#          Andreas Hansson
41
42from m5.objects.System import System
43from m5.params import *
44from m5.proxy import *
45from m5.SimObject import SimObject
46
47from m5.objects.ClockedObject import ClockedObject
48
49class BaseXBar(ClockedObject):
50    type = 'BaseXBar'
51    abstract = True
52    cxx_header = "mem/xbar.hh"
53
54    slave = VectorSlavePort("Vector port for connecting masters")
55    master = VectorMasterPort("Vector port for connecting slaves")
56
57    # Latencies governing the time taken for the variuos paths a
58    # packet has through the crossbar. Note that the crossbar itself
59    # does not add the latency due to assumptions in the coherency
60    # mechanism. Instead the latency is annotated on the packet and
61    # left to the neighbouring modules.
62    #
63    # A request incurs the frontend latency, possibly snoop filter
64    # lookup latency, and forward latency. A response incurs the
65    # response latency. Frontend latency encompasses arbitration and
66    # deciding what to do when a request arrives. the forward latency
67    # is the latency involved once a decision is made to forward the
68    # request. The response latency, is similar to the forward
69    # latency, but for responses rather than requests.
70    frontend_latency = Param.Cycles("Frontend latency")
71    forward_latency = Param.Cycles("Forward latency")
72    response_latency = Param.Cycles("Response latency")
73
74    # Width governing the throughput of the crossbar
75    width = Param.Unsigned("Datapath width per port (bytes)")
76
77    # The default port can be left unconnected, or be used to connect
78    # a default slave port
79    default = MasterPort("Port for connecting an optional default slave")
80
81    # The default port can be used unconditionally, or based on
82    # address range, in which case it may overlap with other
83    # ports. The default range is always checked first, thus creating
84    # a two-level hierarchical lookup. This is useful e.g. for the PCI
85    # xbar configuration.
86    use_default_range = Param.Bool(False, "Perform address mapping for " \
87                                       "the default port")
88
89class NoncoherentXBar(BaseXBar):
90    type = 'NoncoherentXBar'
91    cxx_header = "mem/noncoherent_xbar.hh"
92
93class CoherentXBar(BaseXBar):
94    type = 'CoherentXBar'
95    cxx_header = "mem/coherent_xbar.hh"
96
97    # The coherent crossbar additionally has snoop responses that are
98    # forwarded after a specific latency.
99    snoop_response_latency = Param.Cycles("Snoop response latency")
100
101    # An optional snoop filter
102    snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
103
104    # Maximum number of outstanding snoop requests for sanity checks
105    max_outstanding_snoops = Param.Int(512, "Max. outstanding snoops allowed")
106
107    # Maximum routing table size for sanity checks
108    max_routing_table_size = Param.Int(512, "Max. routing table size")
109
110    # Determine how this crossbar handles packets where caches have
111    # already committed to responding, by establishing if the crossbar
112    # is the point of coherency or not.
113    point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
114                                    "point of coherency")
115
116    # Specify whether this crossbar is the point of unification.
117    point_of_unification = Param.Bool(False, "Consider this crossbar the " \
118                                      "point of unification")
119
120    system = Param.System(Parent.any, "System that the crossbar belongs to.")
121
122class SnoopFilter(SimObject):
123    type = 'SnoopFilter'
124    cxx_header = "mem/snoop_filter.hh"
125
126    # Lookup latency of the snoop filter, added to requests that pass
127    # through a coherent crossbar.
128    lookup_latency = Param.Cycles(1, "Lookup latency")
129
130    system = Param.System(Parent.any, "System that the crossbar belongs to.")
131
132    # Sanity check on max capacity to track, adjust if needed.
133    max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
134
135# We use a coherent crossbar to connect multiple masters to the L2
136# caches. Normally this crossbar would be part of the cache itself.
137class L2XBar(CoherentXBar):
138    # 256-bit crossbar by default
139    width = 32
140
141    # Assume that most of this is covered by the cache latencies, with
142    # no more than a single pipeline stage for any packet.
143    frontend_latency = 1
144    forward_latency = 0
145    response_latency = 1
146    snoop_response_latency = 1
147
148    # Use a snoop-filter by default, and set the latency to zero as
149    # the lookup is assumed to overlap with the frontend latency of
150    # the crossbar
151    snoop_filter = SnoopFilter(lookup_latency = 0)
152
153    # This specialisation of the coherent crossbar is to be considered
154    # the point of unification, it connects the dcache and the icache
155    # to the first level of unified cache.
156    point_of_unification = True
157
158# One of the key coherent crossbar instances is the system
159# interconnect, tying together the CPU clusters, GPUs, and any I/O
160# coherent masters, and DRAM controllers.
161class SystemXBar(CoherentXBar):
162    # 128-bit crossbar by default
163    width = 16
164
165    # A handful pipeline stages for each portion of the latency
166    # contributions.
167    frontend_latency = 3
168    forward_latency = 4
169    response_latency = 2
170    snoop_response_latency = 4
171
172    # Use a snoop-filter by default
173    snoop_filter = SnoopFilter(lookup_latency = 1)
174
175    # This specialisation of the coherent crossbar is to be considered
176    # the point of coherency, as there are no (coherent) downstream
177    # caches.
178    point_of_coherency = True
179
180    # This specialisation of the coherent crossbar is to be considered
181    # the point of unification, it connects the dcache and the icache
182    # to the first level of unified cache. This is needed for systems
183    # without caches where the SystemXBar is also the point of
184    # unification.
185    point_of_unification = True
186
187# In addition to the system interconnect, we typically also have one
188# or more on-chip I/O crossbars. Note that at some point we might want
189# to also define an off-chip I/O crossbar such as PCIe.
190class IOXBar(NoncoherentXBar):
191    # 128-bit crossbar by default
192    width = 16
193
194    # Assume a simpler datapath than a coherent crossbar, incuring
195    # less pipeline stages for decision making and forwarding of
196    # requests.
197    frontend_latency = 2
198    forward_latency = 1
199    response_latency = 2
200