112097Sandreas.sandberg@arm.com# Copyright (c) 2012 The Regents of The University of Michigan 212097Sandreas.sandberg@arm.com# Copyright (c) 2016 Centre National de la Recherche Scientifique 312097Sandreas.sandberg@arm.com# All rights reserved. 412097Sandreas.sandberg@arm.com# 512097Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without 612097Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are 712097Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright 812097Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer; 912097Sandreas.sandberg@arm.com# redistributions in binary form must reproduce the above copyright 1012097Sandreas.sandberg@arm.com# notice, this list of conditions and the following disclaimer in the 1112097Sandreas.sandberg@arm.com# documentation and/or other materials provided with the distribution; 1212097Sandreas.sandberg@arm.com# neither the name of the copyright holders nor the names of its 1312097Sandreas.sandberg@arm.com# contributors may be used to endorse or promote products derived from 1412097Sandreas.sandberg@arm.com# this software without specific prior written permission. 1512097Sandreas.sandberg@arm.com# 1612097Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712097Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812097Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912097Sandreas.sandberg@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012097Sandreas.sandberg@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112097Sandreas.sandberg@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212097Sandreas.sandberg@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312097Sandreas.sandberg@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412097Sandreas.sandberg@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512097Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612097Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712097Sandreas.sandberg@arm.com# 2812097Sandreas.sandberg@arm.com# Authors: Ron Dreslinski 2912097Sandreas.sandberg@arm.com# Anastasiia Butko 3012097Sandreas.sandberg@arm.com# Louisa Bessad 3112097Sandreas.sandberg@arm.com 3213774Sandreas.sandberg@arm.comfrom __future__ import print_function 3313774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 3413774Sandreas.sandberg@arm.com 3512097Sandreas.sandberg@arm.comfrom m5.objects import * 3612097Sandreas.sandberg@arm.com 3712097Sandreas.sandberg@arm.com#----------------------------------------------------------------------- 3812097Sandreas.sandberg@arm.com# ex5 LITTLE core (based on the ARM Cortex-A7) 3912097Sandreas.sandberg@arm.com#----------------------------------------------------------------------- 4012097Sandreas.sandberg@arm.com 4112097Sandreas.sandberg@arm.com# Simple ALU Instructions have a latency of 3 4212097Sandreas.sandberg@arm.comclass ex5_LITTLE_Simple_Int(MinorDefaultIntFU): 4312097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IntAlu', opLat=4) ] 4412097Sandreas.sandberg@arm.com 4512097Sandreas.sandberg@arm.com# Complex ALU instructions have a variable latencies 4612097Sandreas.sandberg@arm.comclass ex5_LITTLE_Complex_IntMul(MinorDefaultIntMulFU): 4712097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IntMult', opLat=7) ] 4812097Sandreas.sandberg@arm.com 4912097Sandreas.sandberg@arm.comclass ex5_LITTLE_Complex_IntDiv(MinorDefaultIntDivFU): 5012097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IntDiv', opLat=9) ] 5112097Sandreas.sandberg@arm.com 5212097Sandreas.sandberg@arm.com# Floating point and SIMD instructions 5312097Sandreas.sandberg@arm.comclass ex5_LITTLE_FP(MinorDefaultFloatSimdFU): 5412097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='SimdAdd', opLat=6), 5512097Sandreas.sandberg@arm.com OpDesc(opClass='SimdAddAcc', opLat=4), 5612097Sandreas.sandberg@arm.com OpDesc(opClass='SimdAlu', opLat=4), 5712097Sandreas.sandberg@arm.com OpDesc(opClass='SimdCmp', opLat=1), 5812097Sandreas.sandberg@arm.com OpDesc(opClass='SimdCvt', opLat=3), 5912097Sandreas.sandberg@arm.com OpDesc(opClass='SimdMisc', opLat=3), 6012097Sandreas.sandberg@arm.com OpDesc(opClass='SimdMult',opLat=4), 6112097Sandreas.sandberg@arm.com OpDesc(opClass='SimdMultAcc',opLat=5), 6212097Sandreas.sandberg@arm.com OpDesc(opClass='SimdShift',opLat=3), 6312097Sandreas.sandberg@arm.com OpDesc(opClass='SimdShiftAcc', opLat=3), 6412097Sandreas.sandberg@arm.com OpDesc(opClass='SimdSqrt', opLat=9), 6512097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatAdd',opLat=8), 6612097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatAlu',opLat=6), 6712097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatCmp', opLat=6), 6812097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatCvt', opLat=6), 6912097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatDiv', opLat=20, pipelined=False), 7012097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatMisc', opLat=6), 7112097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatMult', opLat=15), 7212097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatMultAcc',opLat=6), 7312097Sandreas.sandberg@arm.com OpDesc(opClass='SimdFloatSqrt', opLat=17), 7412097Sandreas.sandberg@arm.com OpDesc(opClass='FloatAdd', opLat=8), 7512097Sandreas.sandberg@arm.com OpDesc(opClass='FloatCmp', opLat=6), 7612097Sandreas.sandberg@arm.com OpDesc(opClass='FloatCvt', opLat=6), 7712097Sandreas.sandberg@arm.com OpDesc(opClass='FloatDiv', opLat=15, pipelined=False), 7812097Sandreas.sandberg@arm.com OpDesc(opClass='FloatSqrt', opLat=33), 7912097Sandreas.sandberg@arm.com OpDesc(opClass='FloatMult', opLat=6) ] 8012097Sandreas.sandberg@arm.com 8112097Sandreas.sandberg@arm.com# Load/Store Units 8212097Sandreas.sandberg@arm.comclass ex5_LITTLE_MemFU(MinorDefaultMemFU): 8312097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='MemRead',opLat=1), 8412097Sandreas.sandberg@arm.com OpDesc(opClass='MemWrite',opLat=1) ] 8512097Sandreas.sandberg@arm.com 8612097Sandreas.sandberg@arm.com# Misc Unit 8712097Sandreas.sandberg@arm.comclass ex5_LITTLE_MiscFU(MinorDefaultMiscFU): 8812097Sandreas.sandberg@arm.com opList = [ OpDesc(opClass='IprAccess',opLat=1), 8912097Sandreas.sandberg@arm.com OpDesc(opClass='InstPrefetch',opLat=1) ] 9012097Sandreas.sandberg@arm.com 9112097Sandreas.sandberg@arm.com# Functional Units for this CPU 9212097Sandreas.sandberg@arm.comclass ex5_LITTLE_FUP(MinorFUPool): 9312097Sandreas.sandberg@arm.com funcUnits = [ex5_LITTLE_Simple_Int(), ex5_LITTLE_Simple_Int(), 9412097Sandreas.sandberg@arm.com ex5_LITTLE_Complex_IntMul(), ex5_LITTLE_Complex_IntDiv(), 9512097Sandreas.sandberg@arm.com ex5_LITTLE_FP(), ex5_LITTLE_MemFU(), 9612097Sandreas.sandberg@arm.com ex5_LITTLE_MiscFU()] 9712097Sandreas.sandberg@arm.com 9812097Sandreas.sandberg@arm.comclass ex5_LITTLE(MinorCPU): 9912097Sandreas.sandberg@arm.com executeFuncUnits = ex5_LITTLE_FUP() 10012097Sandreas.sandberg@arm.com 10112097Sandreas.sandberg@arm.comclass L1Cache(Cache): 10212097Sandreas.sandberg@arm.com tag_latency = 2 10312097Sandreas.sandberg@arm.com data_latency = 2 10412097Sandreas.sandberg@arm.com response_latency = 2 10512097Sandreas.sandberg@arm.com tgts_per_mshr = 8 10612097Sandreas.sandberg@arm.com # Consider the L2 a victim cache also for clean lines 10712097Sandreas.sandberg@arm.com writeback_clean = True 10812097Sandreas.sandberg@arm.com 10912097Sandreas.sandberg@arm.comclass L1I(L1Cache): 11012097Sandreas.sandberg@arm.com mshrs = 2 11112097Sandreas.sandberg@arm.com size = '32kB' 11212097Sandreas.sandberg@arm.com assoc = 2 11312097Sandreas.sandberg@arm.com is_read_only = True 11412097Sandreas.sandberg@arm.com tgts_per_mshr = 20 11512097Sandreas.sandberg@arm.com 11612097Sandreas.sandberg@arm.comclass L1D(L1Cache): 11712097Sandreas.sandberg@arm.com mshrs = 4 11812097Sandreas.sandberg@arm.com size = '32kB' 11912097Sandreas.sandberg@arm.com assoc = 4 12012097Sandreas.sandberg@arm.com write_buffers = 4 12112097Sandreas.sandberg@arm.com 12212097Sandreas.sandberg@arm.com# TLB Cache 12312097Sandreas.sandberg@arm.com# Use a cache as a L2 TLB 12412097Sandreas.sandberg@arm.comclass WalkCache(Cache): 12512097Sandreas.sandberg@arm.com tag_latency = 2 12612097Sandreas.sandberg@arm.com data_latency = 2 12712097Sandreas.sandberg@arm.com response_latency = 2 12812097Sandreas.sandberg@arm.com mshrs = 6 12912097Sandreas.sandberg@arm.com tgts_per_mshr = 8 13012097Sandreas.sandberg@arm.com size = '1kB' 13112097Sandreas.sandberg@arm.com assoc = 2 13212097Sandreas.sandberg@arm.com write_buffers = 16 13312097Sandreas.sandberg@arm.com is_read_only = True 13412097Sandreas.sandberg@arm.com # Writeback clean lines as well 13512097Sandreas.sandberg@arm.com writeback_clean = True 13612097Sandreas.sandberg@arm.com 13712097Sandreas.sandberg@arm.com# L2 Cache 13812097Sandreas.sandberg@arm.comclass L2(Cache): 13912097Sandreas.sandberg@arm.com tag_latency = 9 14012097Sandreas.sandberg@arm.com data_latency = 9 14112097Sandreas.sandberg@arm.com response_latency = 9 14212097Sandreas.sandberg@arm.com mshrs = 8 14312097Sandreas.sandberg@arm.com tgts_per_mshr = 12 14412097Sandreas.sandberg@arm.com size = '512kB' 14512097Sandreas.sandberg@arm.com assoc = 8 14612097Sandreas.sandberg@arm.com write_buffers = 16 14712097Sandreas.sandberg@arm.com prefetch_on_access = True 14812097Sandreas.sandberg@arm.com clusivity = 'mostly_excl' 14912097Sandreas.sandberg@arm.com # Simple stride prefetcher 15012097Sandreas.sandberg@arm.com prefetcher = StridePrefetcher(degree=1, latency = 1) 15112600Sodanrc@yahoo.com.br tags = BaseSetAssoc() 15214216Sodanrc@yahoo.com.br replacement_policy = RandomRP() 153