| /gem5/src/arch/generic/ |
| H A D | tlb.hh | 59 enum Mode { Read, Write, Execute }; enum in class:BaseTLB
79 ThreadContext *tc, Mode mode) = 0;
93 const RequestPtr &req, ThreadContext *tc, Mode mode) = 0;
96 Translation *translation, Mode mode) = 0;
98 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode)
118 const RequestPtr &req, ThreadContext *tc, Mode mode) const = 0;
155 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
158 Translation *translation, Mode mode) override;
161 const RequestPtr &req, ThreadContext *tc, Mode mode) const override;
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| H A D | tlb.cc | 40 GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode)
56 Translation *translation, Mode mode)
64 Mode mode) const
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| /gem5/src/arch/arm/ |
| H A D | stage2_lookup.hh | 66 BaseTLB::Mode mode;
78 TLB::Translation *_transState, BaseTLB::Mode _mode, bool _timing,
92 void mergeTe(const RequestPtr &req, BaseTLB::Mode mode);
101 BaseTLB::Mode mode);
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| H A D | tlb.hh | 81 BaseTLB::Mode mode,
97 Addr is_priv, BaseTLB::Mode mode,
235 ThreadContext *tc, Mode mode,
240 ThreadContext *tc, Mode mode,
244 Fault checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode);
245 Fault checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
248 Mode mode);
301 Fault trickBoxCheck(const RequestPtr &req, Mode mode,
332 Mode mode, ArmTranslationType tranType);
335 ThreadContext *tc, Mode mod
[all...] |
| H A D | stage2_mmu.hh | 91 BaseTLB::Mode mode);
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| H A D | stage2_lookup.cc | 82 Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode)
180 ThreadContext *tc, BaseTLB::Mode mode)
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| H A D | stage2_mmu.cc | 122 ThreadContext *tc, BaseTLB::Mode mode)
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| H A D | tlb.cc | 137 ThreadContext *tc, Mode mode) const
565 TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode,
605 TLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode)
783 TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
1016 TLB::checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode)
1036 TLB::translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode,
1200 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode,
1221 TLB::translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode,
1243 Translation *translation, Mode mode, TLB::ArmTranslationType tranType)
1260 Translation *translation, Mode mod
[all...] |
| /gem5/src/arch/x86/ |
| H A D | tlb.hh | 112 Translation *translation, Mode mode,
126 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
129 Translation *translation, Mode mode) override;
145 Mode mode) const override;
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| H A D | pagetable_walker.hh | 109 BaseTLB::Mode mode;
125 void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
163 const RequestPtr &req, BaseTLB::Mode mode);
165 unsigned &logBytes, BaseTLB::Mode mode);
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| H A D | tlb.cc | 228 ThreadContext *tc, Mode mode) const
271 Mode mode, bool &delayedResponse, bool timing)
430 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
438 Translation *translation, Mode mode)
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| /gem5/src/arch/mips/ |
| H A D | tlb.hh | 116 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
119 Translation *translation, Mode mode) override;
122 ThreadContext *tc, Mode mode) const override;
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| H A D | tlb.cc | 315 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
325 Translation *translation, Mode mode)
333 ThreadContext *tc, Mode mode) const
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| /gem5/src/arch/riscv/ |
| H A D | tlb.hh | 115 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
118 Translation *translation, Mode mode) override;
121 ThreadContext *tc, Mode mode) const override;
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| H A D | tlb.cc | 368 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
378 Translation *translation, Mode mode)
386 ThreadContext *tc, Mode mode) const
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| /gem5/src/cpu/ |
| H A D | translation.hh | 75 BaseTLB::Mode mode;
82 uint64_t *_res, BaseTLB::Mode _mode)
97 uint64_t *_res, BaseTLB::Mode _mode)
253 BaseTLB::Mode mode)
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| /gem5/src/gpu-compute/ |
| H A D | gpu_tlb.hh | 98 typedef enum BaseTLB::Mode Mode; typedef in class:X86ISA::GpuTLB
117 ThreadContext *tc, Mode mode) = 0;
183 Translation *translation, Mode mode, bool &delayedResponse,
226 Mode mode, int &latency);
229 Translation *translation, Mode mode,
251 TlbEntry *tlb_entry, Mode mode);
333 Mode tlbMode;
357 TranslationState(Mode tlb_mode, ThreadContext *_tc,
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| H A D | shader.hh | 196 void functionalTLBAccess(PacketPtr pkt, int cu_id, BaseTLB::Mode mode);
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| /gem5/src/arch/alpha/ |
| H A D | tlb.hh | 145 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
148 Translation *translation, Mode mode) override;
151 Mode mode) const override;
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| /gem5/src/arch/power/ |
| H A D | tlb.hh | 166 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
169 Translation *translation, Mode mode) override;
172 ThreadContext *tc, Mode mode) const override;
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| H A D | tlb.cc | 313 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
326 Translation *translation, Mode mode)
334 ThreadContext *tc, Mode mode) const
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| /gem5/src/arch/sparc/ |
| H A D | tlb.hh | 172 const RequestPtr &req, ThreadContext *tc, Mode mode) override;
175 Translation *translation, Mode mode) override;
178 ThreadContext *tc, Mode mode) const override;
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| /gem5/src/cpu/minor/ |
| H A D | lsq.hh | 283 ThreadContext *tc, BaseTLB::Mode mode)
344 ThreadContext *tc, BaseTLB::Mode mode);
417 ThreadContext *tc, BaseTLB::Mode mode);
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| H A D | fetch1.hh | 167 ThreadContext *tc, BaseTLB::Mode mode);
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| /gem5/src/mem/cache/prefetch/ |
| H A D | queued.hh | 125 ThreadContext *tc, BaseTLB::Mode mode) override;
|