Searched refs:port (Results 51 - 75 of 196) sorted by relevance

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/gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_ports/
H A Dtlm_event_finder.h72 dynamic_cast<const IF*>( port().get_interface() );
74 report_error( sc_core::SC_ID_FIND_EVENT_, "port is not bound" );
84 const IF* iface = dynamic_cast<const IF*>( port().get_interface() );
86 report_error( sc_core::SC_ID_FIND_EVENT_, "port is not bound" );
/gem5/src/cpu/testers/directedtest/
H A DSeriesRequestGenerator.cc58 MasterPort* port = m_directed_tester->getCpuPort(m_active_node); local
76 if (port->sendTimingReq(pkt)) {
/gem5/src/arch/arm/
H A Dstage2_mmu.hh62 DmaPort port; member in class:ArmISA::Stage2MMU
109 * Get the port that ultimately belongs to the stage-two MMU, but
113 DmaPort& getDMAPort() { return port; }
H A Dstage2_mmu.cc53 port(_stage1Tlb->getTableWalker(), p->sys),
56 // we use the stage-one table walker as the parent of the port,
83 port.sendFunctional(&pkt);
85 port.sendAtomic(&pkt);
/gem5/tests/configs/
H A Dmemtest.py64 cpu.l1c.cpu_side = cpu.port
70 system.physmem.port = system.membus.master
H A Dmemtest-filter.py65 cpu.l1c.cpu_side = cpu.port
71 system.physmem.port = system.membus.master
H A Do3-timing-mp-ruby.py55 system.physmem.port = system.membus.master
57 # Connect the system port for loading of binaries etc
H A Dsimple-atomic-mp-ruby.py53 system.physmem.port = system.membus.master
55 # Connect the system port for loading of binaries etc
H A Dt1000-simple-atomic.py55 system.physmem[i].port = system.membus.master
/gem5/tests/gem5/memory/
H A Dmemtest-run.py65 cpu.l1c.cpu_side = cpu.port
71 system.physmem.port = system.membus.master
H A Dsimple-run.py81 system.cpu.port = system.monitor.slave
84 # connect the system port even if it is not used in this example
88 system.physmem.port = system.membus.master
/gem5/src/systemc/core/
H A Dsensitivity.cc33 #include "systemc/core/port.hh"
143 Port *port = Port::fromPort(pb); local
144 port->sensitive(s);
160 Port *port = Port::fromPort(f->port()); local
161 port->sensitive(s);
/gem5/src/mem/
H A Dsnoop_filter.hh53 #include "mem/port.hh"
60 * This snoop filter keeps track of which connected port has a
114 // no need to track this port if it is not snooping
128 * Lookup a request (from a slave port) in the snoop filter and
136 * @param slave_port Slave port where the request came from.
154 * Handle an incoming snoop from below (the master port). These
243 * Convert a single port to a corresponding, one-hot bitmask
244 * @param port SlavePort that should be converted.
245 * @return One-hot bitmask corresponding to the port.
247 SnoopMask portToMask(const SlavePort& port) cons
[all...]
H A Dse_translating_port_proxy.hh62 * simulated system. Via the port proxies all the accesses go through
63 * an actual port and thus are transparent to a potentially
85 SETranslatingPortProxy(MasterPort &port, Process* p, AllocType alloc);
/gem5/src/sim/
H A Dcxx_manager.cc346 const CxxConfigDirectoryEntry::PortDesc *port = (*i).second; local
349 if (!configFile.getPortPeers(object_name, port->name, peers)) {
352 instance_name, port->name);
362 if (!object_params->setPortConnectionCount(port->name,
366 "Unconnected port: %s", port->name));
369 DPRINTF(CxxConfig, "Setting port connection count"
371 instance_name, port->name, peer_count);
455 * defined for port, need getPortConnectionCount and a
466 "Master port
485 bindMasterPort(SimObject *object, const CxxConfigDirectoryEntry::PortDesc &port, const std::vector<std::string> &peers) argument
535 const CxxConfigDirectoryEntry::PortDesc *port = (*i).second; local
558 parsePort(const std::string &inp, std::string &path, std::string &port, unsigned int &index) argument
[all...]
/gem5/util/term/
H A Dterm.c62 char *host, *port, *endp; local
69 port = NULL;
77 port = argv[1];
80 port = argv[2];
96 s = remote_connect(host, port, hints);
109 * port or source address if needed. Return's -1 on failure.
112 remote_connect(char *host, char *port, struct addrinfo hints) argument
117 if ((error = getaddrinfo(host, port, &hints, &res)))
224 fprintf(stderr, "usage: %s hostname port\n", progname);
/gem5/src/mem/qos/
H A Dmem_sink.cc52 writeBufferSize(p->write_buffer_size), port(name() + ".port", *this),
71 if (port.isConnected()) {
72 port.sendRangeChange();
112 if (interface != "port") {
115 return port;
152 // Remember that we have to retry this port
166 // Remember that we have to retry this port
265 // hands over control to the port
292 port
[all...]
/gem5/src/dev/serial/
H A Dterminal.cc132 if (p->port)
133 listen(p->port);
170 Terminal::listen(int port) argument
177 while (!listener.listen(port, true)) {
179 ": can't bind address terminal port %d inuse PID %d\n",
180 port, getpid());
181 port++;
184 ccprintf(cerr, "%s: Listening for connections on port %d\n",
185 name(), port);
/gem5/util/tlm/src/
H A Dsim_control.cc81 // register the systemc slave and master port handler
181 Gem5SimControl::registerSlavePort(const std::string& name, SCSlavePort* port) argument
184 slavePorts[name] = port;
192 Gem5SimControl::registerMasterPort(const std::string& name, SCMasterPort* port) argument
195 masterPorts[name] = port;
/gem5/src/systemc/channel/
H A Dsc_signal.cc114 WriteChecker<sc_core::SC_ONE_WRITER>::checkPort(sc_core::sc_port_base &port, argument
119 reportSignalError(sig, firstPort, &port);
120 firstPort = &port;
142 WriteChecker<sc_core::SC_MANY_WRITERS>::checkPort(sc_core::sc_port_base &port, argument
/gem5/configs/common/
H A DMemConfig.py183 port=system.membus.master,
191 port_data="init_mem0", port=xbar.master,
244 subsystem.mem_ctrls[i].port = xbar[i/4].master
249 subsystem.mem_ctrls[i].port = xbar.master
/gem5/src/base/
H A Dsocket.cc90 ListenSocket::listen(int port, bool reuse) argument
110 sockaddr.sin_port = htons(port);
/gem5/src/mem/ruby/network/garnet2.0/
H A Dflit.hh65 void set_outport(int port) { m_outport = port; } argument
/gem5/src/cpu/testers/rubytest/
H A DCheck.cc87 MasterPort* port = m_tester_ptr->getReadableCpuPort(index); local
125 if (port->sendTimingReq(pkt)) {
144 MasterPort* port = m_tester_ptr->getWritableCpuPort(index); local
161 if (port->sendTimingReq(pkt)) {
173 MasterPort* port = m_tester_ptr->getWritableCpuPort(index); local
206 if (port->sendTimingReq(pkt)) {
233 MasterPort* port = m_tester_ptr->getReadableCpuPort(index); local
259 if (port->sendTimingReq(pkt)) {
272 DPRINTF(RubyTest, "failed to initiate check - cpu port not ready\n");
/gem5/src/dev/x86/
H A DPc.py39 def x86IOAddress(port):
41 return IO_address_space_base + port;
65 # Serial port and terminal

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