16145SN/A/*
26386SN/A * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
37553SN/A * Copyright (c) 2009-2010 Advanced Micro Devices, Inc.
46386SN/A * All rights reserved.
56386SN/A *
66386SN/A * Redistribution and use in source and binary forms, with or without
76386SN/A * modification, are permitted provided that the following conditions are
86386SN/A * met: redistributions of source code must retain the above copyright
96386SN/A * notice, this list of conditions and the following disclaimer;
106386SN/A * redistributions in binary form must reproduce the above copyright
116386SN/A * notice, this list of conditions and the following disclaimer in the
126386SN/A * documentation and/or other materials provided with the distribution;
136386SN/A * neither the name of the copyright holders nor the names of its
146386SN/A * contributors may be used to endorse or promote products derived from
156386SN/A * this software without specific prior written permission.
166386SN/A *
176386SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
186386SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
196386SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
206386SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
216386SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
226386SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
236386SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
246386SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
256386SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
266386SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
276386SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
286386SN/A */
296145SN/A
3011793Sbrandon.potter@amd.com#include "cpu/testers/directedtest/SeriesRequestGenerator.hh"
3111793Sbrandon.potter@amd.com
3210348Sandreas.hansson@arm.com#include "base/random.hh"
3311800Sbrandon.potter@amd.com#include "base/trace.hh"
347632SBrad.Beckmann@amd.com#include "cpu/testers/directedtest/DirectedGenerator.hh"
357632SBrad.Beckmann@amd.com#include "cpu/testers/directedtest/RubyDirectedTester.hh"
368232Snate@binkert.org#include "debug/DirectedTest.hh"
376145SN/A
387553SN/ASeriesRequestGenerator::SeriesRequestGenerator(const Params *p)
399365Snilay@cs.wisc.edu    : DirectedGenerator(p),
409365Snilay@cs.wisc.edu      m_addr_increment_size(p->addr_increment_size),
419365Snilay@cs.wisc.edu      m_percent_writes(p->percent_writes)
426145SN/A{
437553SN/A    m_status = SeriesRequestGeneratorStatus_Thinking;
447553SN/A    m_active_node = 0;
457553SN/A    m_address = 0x0;
466145SN/A}
476145SN/A
487553SN/ASeriesRequestGenerator::~SeriesRequestGenerator()
496145SN/A{
506145SN/A}
516145SN/A
527553SN/Abool
537553SN/ASeriesRequestGenerator::initiate()
546145SN/A{
557553SN/A    DPRINTF(DirectedTest, "initiating request\n");
567553SN/A    assert(m_status == SeriesRequestGeneratorStatus_Thinking);
576145SN/A
588950Sandreas.hansson@arm.com    MasterPort* port = m_directed_tester->getCpuPort(m_active_node);
597553SN/A
607553SN/A    Request::Flags flags;
617553SN/A
627553SN/A    // For simplicity, requests are assumed to be 1 byte-sized
6312749Sgiacomo.travaglini@arm.com    RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId);
647553SN/A
657553SN/A    Packet::Command cmd;
6610348Sandreas.hansson@arm.com    bool do_write = (random_mt.random(0, 100) < m_percent_writes);
679365Snilay@cs.wisc.edu    if (do_write) {
687553SN/A        cmd = MemCmd::WriteReq;
697553SN/A    } else {
707553SN/A        cmd = MemCmd::ReadReq;
716145SN/A    }
729365Snilay@cs.wisc.edu
738949Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(req, cmd);
7410566Sandreas.hansson@arm.com    pkt->allocate();
756145SN/A
768975Sandreas.hansson@arm.com    if (port->sendTimingReq(pkt)) {
777553SN/A        DPRINTF(DirectedTest, "initiating request - successful\n");
787553SN/A        m_status = SeriesRequestGeneratorStatus_Request_Pending;
797553SN/A        return true;
807553SN/A    } else {
817553SN/A        // If the packet did not issue, must delete
827553SN/A        // Note: No need to delete the data, the packet destructor
837553SN/A        // will delete it
847553SN/A        delete pkt;
857553SN/A
867553SN/A        DPRINTF(DirectedTest, "failed to initiate request - sequencer not ready\n");
877553SN/A        return false;
887553SN/A    }
896145SN/A}
906145SN/A
9111320Ssteve.reinhardt@amd.comvoid
928655Sandreas.hansson@arm.comSeriesRequestGenerator::performCallback(uint32_t proc, Addr address)
936145SN/A{
947553SN/A    assert(m_active_node == proc);
9511320Ssteve.reinhardt@amd.com    assert(m_address == address);
967553SN/A    assert(m_status == SeriesRequestGeneratorStatus_Request_Pending);
976145SN/A
987553SN/A    m_status = SeriesRequestGeneratorStatus_Thinking;
997553SN/A    m_active_node++;
1007553SN/A    if (m_active_node == m_num_cpus) {
1017553SN/A        //
1027553SN/A        // Cycle of requests completed, increment cycle completions and restart
1037553SN/A        // at cpu zero
1047553SN/A        //
1057553SN/A        m_directed_tester->incrementCycleCompletions();
1067553SN/A        m_address += m_addr_increment_size;
1077553SN/A        m_active_node = 0;
1087553SN/A    }
1096145SN/A}
1106145SN/A
1117553SN/ASeriesRequestGenerator *
1127553SN/ASeriesRequestGeneratorParams::create()
1136145SN/A{
1147553SN/A    return new SeriesRequestGenerator(this);
1156145SN/A}
116