Searched defs:req (Results 1 - 25 of 85) sorted by relevance

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/gem5/src/arch/arm/
H A Dstage2_lookup.cc82 Stage2LookUp::mergeTe(const RequestPtr &req, BaseTLB::Mode mode) argument
179 Stage2LookUp::finish(const Fault &_fault, const RequestPtr &req, argument
H A Dvtophys.cc73 auto req = std::make_shared<Request>(0, addr, 64, 0x40, -1, 0, 0); local
H A Dlocked_mem.hh94 handleLockedRead(XC *xc, const RequestPtr &req) argument
114 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
H A Dstage2_mmu.cc70 auto req = std::make_shared<Request>(); local
120 finish(const Fault &_fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode) argument
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H A Dstage2_mmu.hh75 RequestPtr req; member in class:ArmISA::Stage2MMU::Stage2Translation
/gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_adapters/
H A Dtlm_adapters.h88 REQ req; local
/gem5/src/arch/alpha/
H A Dlocked_mem.hh88 handleLockedRead(XC *xc, const RequestPtr &req) argument
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
/gem5/src/arch/generic/
H A Dlocked_mem.hh66 handleLockedRead(XC *xc, const RequestPtr &req) argument
79 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
H A Dtlb.cc40 GenericTLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode) argument
55 GenericTLB::translateTiming(const RequestPtr &req, ThreadContext *tc, argument
59 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); local
63 GenericTLB::finalizePhysical(const RequestPtr &req, ThreadContext *tc, argument
H A Dtlb.hh98 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode) argument
/gem5/src/arch/mips/
H A Dlocked_mem.hh78 handleLockedRead(XC *xc, const RequestPtr &req) argument
95 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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/gem5/src/cpu/testers/directedtest/
H A DSeriesRequestGenerator.cc63 RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId); local
H A DInvalidateGenerator.cc63 RequestPtr req = std::make_shared<Request>(m_address, 1, flags, masterId); local
/gem5/src/arch/riscv/
H A Dlocked_mem.hh88 handleLockedRead(XC *xc, const RequestPtr &req) argument
102 handleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) argument
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/gem5/src/systemc/ext/tlm_core/1/req_rsp/adapters/
H A Dadapters.hh50 transport(const REQ &req) argument
87 REQ req; local
/gem5/src/mem/
H A Dport_proxy.cc51 auto req = std::make_shared<Request>( local
68 auto req = std::make_shared<Request>( local
H A Dpage_table.cc157 EmulationPageTable::translate(const RequestPtr &req) argument
/gem5/ext/sst/
H A DExtSlave.cc178 RequestPtr req = std::make_shared<Request>( local
H A DExtMaster.cc174 auto req = std::make_shared<Request>(ev->getAddr(), ev->getSize(), flags, 0); local
/gem5/src/dev/virtio/
H A Dblock.cc71 VirtIOBlock::read(const BlkRequest &req, VirtDescriptor *desc_chain, argument
97 VirtIOBlock::write(const BlkRequest &req, VirtDescriptor *desc_chain, argument
133 BlkRequest req; local
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/gem5/src/cpu/testers/traffic_gen/
H A Dbase_gen.cc65 RequestPtr req = std::make_shared<Request>(addr, size, flags, masterID); local
/gem5/src/dev/arm/
H A Drv_ctrl.cc166 CfgCtrlReg req = pkt->getLE<uint32_t>(); local
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/gem5/src/gpu-compute/
H A Dfetch_unit.cc148 RequestPtr req = std::make_shared<Request>( local
[all...]
/gem5/src/systemc/ext/tlm_core/1/req_rsp/channels/req_rsp_channels/
H A Dput_get_imp.hh97 tlm_master_imp(tlm_put_if<REQ> &req, tlm_get_peek_if<RSP> &rsp) : argument
107 tlm_slave_imp(tlm_get_peek_if<REQ> &req, tlm_put_if<RSP> &rsp) : argument
/gem5/src/systemc/ext/tlm_core/1/req_rsp/interfaces/
H A Dcore_ifs.hh36 transport(const REQ &req, RSP &rsp) argument

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