16019Shines@cs.fsu.edu/* 212218Snikos.nikoleris@arm.com * Copyright (c) 2012-2013,2017 ARM Limited 39383SAli.Saidi@ARM.com * All rights reserved 49383SAli.Saidi@ARM.com * 59383SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 69383SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 79383SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 89383SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 99383SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 109383SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 119383SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 129383SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 139383SAli.Saidi@ARM.com * 146019Shines@cs.fsu.edu * Copyright (c) 2006 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 418209SAli.Saidi@ARM.com * Authors: Ali Saidi 428209SAli.Saidi@ARM.com * Steve Reinhardt 436019Shines@cs.fsu.edu * Stephen Hines 446019Shines@cs.fsu.edu */ 456019Shines@cs.fsu.edu 466019Shines@cs.fsu.edu#ifndef __ARCH_ARM_LOCKED_MEM_HH__ 476019Shines@cs.fsu.edu#define __ARCH_ARM_LOCKED_MEM_HH__ 486019Shines@cs.fsu.edu 496019Shines@cs.fsu.edu/** 506019Shines@cs.fsu.edu * @file 516019Shines@cs.fsu.edu * 526019Shines@cs.fsu.edu * ISA-specific helper functions for locked memory accesses. 536019Shines@cs.fsu.edu */ 546019Shines@cs.fsu.edu 558209SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 5610037SARM gem5 Developers#include "arch/arm/isa_traits.hh" 5710037SARM gem5 Developers#include "debug/LLSC.hh" 589383SAli.Saidi@ARM.com#include "mem/packet.hh" 596019Shines@cs.fsu.edu#include "mem/request.hh" 606019Shines@cs.fsu.edu 616019Shines@cs.fsu.edunamespace ArmISA 626019Shines@cs.fsu.edu{ 636019Shines@cs.fsu.edutemplate <class XC> 646019Shines@cs.fsu.eduinline void 659383SAli.Saidi@ARM.comhandleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask) 669383SAli.Saidi@ARM.com{ 6711357Sstephan.diestelhorst@arm.com // Should only every see invalidations / direct writes 6811357Sstephan.diestelhorst@arm.com assert(pkt->isInvalidate() || pkt->isWrite()); 6911357Sstephan.diestelhorst@arm.com 7011357Sstephan.diestelhorst@arm.com DPRINTF(LLSC,"%s: handling snoop for address: %#x locked: %d\n", 7110037SARM gem5 Developers xc->getCpuPtr()->name(),pkt->getAddr(), 7210037SARM gem5 Developers xc->readMiscReg(MISCREG_LOCKFLAG)); 739383SAli.Saidi@ARM.com if (!xc->readMiscReg(MISCREG_LOCKFLAG)) 749383SAli.Saidi@ARM.com return; 759383SAli.Saidi@ARM.com 769383SAli.Saidi@ARM.com Addr locked_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 7710037SARM gem5 Developers // If no caches are attached, the snoop address always needs to be masked 7810030SAli.Saidi@ARM.com Addr snoop_addr = pkt->getAddr() & cacheBlockMask; 799383SAli.Saidi@ARM.com 8011357Sstephan.diestelhorst@arm.com DPRINTF(LLSC,"%s: handling snoop for address: %#x locked addr: %#x\n", 8110037SARM gem5 Developers xc->getCpuPtr()->name(),snoop_addr, locked_addr); 8210037SARM gem5 Developers if (locked_addr == snoop_addr) { 8310037SARM gem5 Developers DPRINTF(LLSC,"%s: address match, clearing lock and signaling sev\n", 8410037SARM gem5 Developers xc->getCpuPtr()->name()); 859383SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 8610037SARM gem5 Developers // Implement ARMv8 WFE/SEV semantics 8710037SARM gem5 Developers xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 8811151Smitch.hayenga@arm.com xc->getCpuPtr()->wakeup(xc->threadId()); 8910037SARM gem5 Developers } 9010030SAli.Saidi@ARM.com} 9110030SAli.Saidi@ARM.com 9210030SAli.Saidi@ARM.comtemplate <class XC> 9310030SAli.Saidi@ARM.cominline void 9412749Sgiacomo.travaglini@arm.comhandleLockedRead(XC *xc, const RequestPtr &req) 956019Shines@cs.fsu.edu{ 9610030SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKADDR, req->getPaddr()); 978209SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, true); 9810037SARM gem5 Developers DPRINTF(LLSC,"%s: Placing address %#x in monitor\n", xc->getCpuPtr()->name(), 9910037SARM gem5 Developers req->getPaddr()); 1006019Shines@cs.fsu.edu} 1016019Shines@cs.fsu.edu 10210037SARM gem5 Developerstemplate <class XC> 10310037SARM gem5 Developersinline void 10410037SARM gem5 DevelopershandleLockedSnoopHit(XC *xc) 10510037SARM gem5 Developers{ 10610037SARM gem5 Developers DPRINTF(LLSC,"%s: handling snoop lock hit address: %#x\n", 10710037SARM gem5 Developers xc->getCpuPtr()->name(), xc->readMiscReg(MISCREG_LOCKADDR)); 10810037SARM gem5 Developers xc->setMiscReg(MISCREG_LOCKFLAG, false); 10910037SARM gem5 Developers xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 11010037SARM gem5 Developers} 1116019Shines@cs.fsu.edu 1126019Shines@cs.fsu.edutemplate <class XC> 1136019Shines@cs.fsu.eduinline bool 11412749Sgiacomo.travaglini@arm.comhandleLockedWrite(XC *xc, const RequestPtr &req, Addr cacheBlockMask) 1156019Shines@cs.fsu.edu{ 1168209SAli.Saidi@ARM.com if (req->isSwap()) 1178209SAli.Saidi@ARM.com return true; 1188209SAli.Saidi@ARM.com 11910037SARM gem5 Developers DPRINTF(LLSC,"%s: handling locked write for address %#x in monitor\n", 12010037SARM gem5 Developers xc->getCpuPtr()->name(), req->getPaddr()); 1218209SAli.Saidi@ARM.com // Verify that the lock flag is still set and the address 1228209SAli.Saidi@ARM.com // is correct 1238209SAli.Saidi@ARM.com bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG); 12410030SAli.Saidi@ARM.com Addr lock_addr = xc->readMiscReg(MISCREG_LOCKADDR) & cacheBlockMask; 12510030SAli.Saidi@ARM.com if (!lock_flag || (req->getPaddr() & cacheBlockMask) != lock_addr) { 1268209SAli.Saidi@ARM.com // Lock flag not set or addr mismatch in CPU; 1278209SAli.Saidi@ARM.com // don't even bother sending to memory system 1288209SAli.Saidi@ARM.com req->setExtraData(0); 1298209SAli.Saidi@ARM.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 13010037SARM gem5 Developers DPRINTF(LLSC,"%s: clearing lock flag in handle locked write\n", 13110037SARM gem5 Developers xc->getCpuPtr()->name()); 1328209SAli.Saidi@ARM.com // the rest of this code is not architectural; 1338209SAli.Saidi@ARM.com // it's just a debugging aid to help detect 1348209SAli.Saidi@ARM.com // livelock by warning on long sequences of failed 1358209SAli.Saidi@ARM.com // store conditionals 1368209SAli.Saidi@ARM.com int stCondFailures = xc->readStCondFailures(); 1378209SAli.Saidi@ARM.com stCondFailures++; 1388209SAli.Saidi@ARM.com xc->setStCondFailures(stCondFailures); 1398209SAli.Saidi@ARM.com if (stCondFailures % 100000 == 0) { 1408209SAli.Saidi@ARM.com warn("context %d: %d consecutive " 1418209SAli.Saidi@ARM.com "store conditional failures\n", 1428209SAli.Saidi@ARM.com xc->contextId(), stCondFailures); 1438209SAli.Saidi@ARM.com } 1448209SAli.Saidi@ARM.com 1458209SAli.Saidi@ARM.com // store conditional failed already, so don't issue it to mem 1468209SAli.Saidi@ARM.com return false; 1478209SAli.Saidi@ARM.com } 1486019Shines@cs.fsu.edu return true; 1496019Shines@cs.fsu.edu} 1506019Shines@cs.fsu.edu 15112218Snikos.nikoleris@arm.comtemplate <class XC> 15212218Snikos.nikoleris@arm.cominline void 15312218Snikos.nikoleris@arm.comglobalClearExclusive(XC *xc) 15412218Snikos.nikoleris@arm.com{ 15512218Snikos.nikoleris@arm.com // A spinlock would typically include a Wait For Event (WFE) to 15612218Snikos.nikoleris@arm.com // conserve energy. The ARMv8 architecture specifies that an event 15712218Snikos.nikoleris@arm.com // is automatically generated when clearing the exclusive monitor 15812218Snikos.nikoleris@arm.com // to wake up the processor in WFE. 15912218Snikos.nikoleris@arm.com DPRINTF(LLSC,"Clearing lock and signaling sev\n"); 16012218Snikos.nikoleris@arm.com xc->setMiscReg(MISCREG_LOCKFLAG, false); 16112218Snikos.nikoleris@arm.com // Implement ARMv8 WFE/SEV semantics 16212218Snikos.nikoleris@arm.com xc->setMiscReg(MISCREG_SEV_MAILBOX, true); 16312218Snikos.nikoleris@arm.com xc->getCpuPtr()->wakeup(xc->threadId()); 16412218Snikos.nikoleris@arm.com} 1656019Shines@cs.fsu.edu 1666019Shines@cs.fsu.edu} // namespace ArmISA 1676019Shines@cs.fsu.edu 1686019Shines@cs.fsu.edu#endif 169