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12749:223c83ed9979 |
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04-Jun-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12637:bfc3cb9c7e6c |
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30-Mar-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
mem: Remove unused 'using namespace'
Removal of unused/barely used 'using namespace' from C++ files.
Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a Reviewed-on: https://gem5-review.googlesource.com/9601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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12536:0a1d2ced2d4c |
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19-Feb-2018 |
Brandon Potter <brandon.potter@amd.com> |
mem: fix page_table bug for .fast build
Since b8b13206c8, the '.fast' build has failed to compile with an error caused by a variable and an assert.
As a reminder, assert macros are optimized out of the build for '.fast'. If an assert check requires a variable that is unused anywhere else in the code, the compiler complains that the variable is unused and the scons build fails. The solution is to add a M5_VAR_USED specifier to tell the compiler to ignore the variable.
Change-Id: I38f6bbed1e4c0506c5bbc1206c21f1f7e3d8dfe6 Reviewed-on: https://gem5-review.googlesource.com/8462 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
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12519:1fcc0d0a8f91 |
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13-Feb-2018 |
Rico Amslinger <rico.amslinger@informatik.uni-augsburg.de> |
mem, sim-se: Fixed seg-fault in EmulationPageTable::remap
When moving a memory region the target region should be unmapped. The assertion does reflect this, but the following line accesses the invalid pointer regardless. This commit replaces the pointer access with an emplace.
Change-Id: I85f9be4e6c223eab447c75043e593ed3f90017e1 Reviewed-on: https://gem5-review.googlesource.com/8261 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
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12461:a4cb506cda74 |
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09-Jan-2018 |
Gabe Black <gabeblack@google.com> |
tarch, mem: Abstract the data stored in the SE page tables.
Rather than store the actual TLB entry that corresponds to a mapping, we can just store some abstracted information (address, a few flags) and then let the caller turn that into the appropriate entry. There could potentially be some small amount of overhead from creating entries vs. storing them and just installing them, but it's likely pretty minimal since that only happens on a TLB miss (ideally rare), and, if it is problematic, there could be some preallocated TLB entries which are just minimally filled in as necessary.
This has the nice effect of finally making the page tables ISA agnostic.
Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317 Reviewed-on: https://gem5-review.googlesource.com/7350 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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12460:0f221912b014 |
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08-Jan-2018 |
Gabe Black <gabeblack@google.com> |
x86, mem: Rewrite the multilevel page table class.
The new version extracts all the x86 specific aspects of the class, and builds the interface around a variable collection of template arguments which are classes that represent the different levels of the page table. The multilevel page table class is now much more ISA independent.
Change-Id: Id42e168a78d0e70f80ab2438480cb6e00a3aa636 Reviewed-on: https://gem5-review.googlesource.com/7347 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
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12455:c88f0b37f433 |
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05-Jan-2018 |
Gabe Black <gabeblack@google.com> |
arch, mem: Make the page table lookup function return a pointer.
This avoids having a copy in the lookup function itself, and the declaration of a lot of temporary TLB entry pointers in callers. The gpu TLB seems to have had the most dependence on the original signature of the lookup function, partially because it was relying on a somewhat unsafe copy to a TLB entry using a base class pointer type.
Change-Id: I8b1cf494468163deee000002d243541657faf57f Reviewed-on: https://gem5-review.googlesource.com/7343 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
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12448:b299e560f1d8 |
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04-Jan-2018 |
Gabe Black <gabeblack@google.com> |
arch, mem, sim: Consolidate and rename the SE mode page table classes.
Now that Nothing inherits from PageTableBase directly, it can be merged into FuncPageTable. This change also takes the opportunity to rename the combined class to EmulationPageTable which lets you know that it's specifically for SE mode.
Also remove the page table entry cache since it doesn't seem to actually improve performance. The TLBs likely absorb the majority of the locality, essentially acting like a cache like they would in real hardware.
Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13 Reviewed-on: https://gem5-review.googlesource.com/7342 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
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12442:e003b72b46ac |
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22-Dec-2017 |
Gabe Black <gabeblack@google.com> |
mem: Track TLB entries in the lookup cache as pointers.
Using the architectural page table on x86 and the functional page table on ARM, both with the twolf benchmark in SE mode, there was no performance penalty for doing so, and again possibly a performance improvement. By using a pointer instead of an inline instance, it's possible for the actual type of the TLB entry to be hidden somewhat, taking a step towards abstracting away another aspect of the ISAs.
Since the TLB entries are no longer overwritten and now need to be allocated and freed, this change introduces return types from the updateCache and eraseCacheEntry functions. These functions will return the pointer to any entry which has been displaced from the cache which the caller can either free or ignore, depending on whether the entry has a purpose outside of the cache.
Because the functional page table stores its entries over a longer time period, it will generally not delete the pointer returned from those functions. The "architechtural" page table, ie the one which is backed by memory, doesn't have any other use for the TlbEntrys and will delete them. That leads to more news and deletes than there used to be.
To address that, and also to speed up the architectural page table in general, it would be a good idea to augment the functional page table with an image of the table in memory, instead of replacing it with one. The functional page table would provide quick lookups and also avoid having to translate page table entries to TLB entries, making performance essentially equivalent to the functional case. The backing page tables, which are primarily for consumption by the physical hardware when in KVM, can be updated when mappings change but otherwise left alone.
If we end up doing that, we could just let the ISA specific process classes enable whatever additional TLB machinery they need, likely a backing copy in memory, without any knowledge or involvement from the ISA agnostic class. We would be able to get rid of the useArchPT setting and the bits of code in the configs which set it.
Change-Id: I2e21945cd852bb1b3d0740fe6a4c5acbfd9548c5 Reviewed-on: https://gem5-review.googlesource.com/6983 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
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11886:43b882cada33 |
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27-Feb-2017 |
Brandon Potter <brandon.potter@amd.com> |
syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess simulations
Modifies the clone system call and adds execve system call. Requires allowing processes to steal thread contexts from other processes in the same system object and the ability to detach pieces of process state (such as MemState) to allow dynamic sharing.
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11800:54436a1784dc |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 3/22] reduce include dependencies in some headers
Used cppclean to help identify useless includes and removed them. This involved erroneously included headers, but also cases where forward declarations could have been used rather than a full include.
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11793:ef606668d247 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes
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10905:a6ca6831e775 |
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07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section.
* Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections).
* The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects.
* Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code.
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10558:426665ec11a9 |
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23-Nov-2014 |
Alexandru Dutu <alexandru.dutu@amd.com> |
mem: Page Table map api modification
This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
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10556:1e3b3c7a0cba |
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23-Nov-2014 |
Alexandru Dutu <alexandru.dutu@amd.com> |
mem: Page Table long lines
Trimmed down all the lines greater than 78 characters.
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10298:77af86f37337 |
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01-Apr-2014 |
Alexandru <alexandru.dutu@amd.com> |
mem: adding a multi-level page table class This patch defines a multi-level page table class that stores the page table in system memory, consistent with ISA specifications. In this way, cpu models that use the actual hardware to execute (e.g. KvmCPU), are able to traverse the page table.
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9676:83d5112e71dd |
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23-Apr-2013 |
Mitch Hayenga <mitch.hayenga+gem5@gmail.com> |
sim: Fix two bugs relating to software caching of PageTable entries.
The existing implementation can read uninitialized data or stale information from the cached PageTable entries.
1) Add a valid bit for the cache entries. Simply using zero for the virtual address to signify invalid entries is not sufficient. Speculative, wrong-path accesses frequently access page zero. The current implementation would return a uninitialized TLB entry when address zero was accessed and the PageTable cache entry was invalid.
2) When unmapping/mapping/remaping a page, invalidate the corresponding PageTable cache entry if one already exists.
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9086:496304c8017d |
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09-Jul-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Fix: Address a few benign memory leaks
This patch is the result of static analysis identifying a number of memory leaks. The leaks are all benign as they are a result of not deallocating memory in the desctructor. The fix still has value as it removes false positives in the static analysis.
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8797:3202eb01e01e |
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07-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Another merge with the main repository.
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8795:0909f8ed7aa0 |
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07-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with main repository.
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8766:b0773af78423 |
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30-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Build the base process class in FS.
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8763:509e9bb84dfa |
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16-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Turn on the page table class in FS.
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8641:4d3ecac1abec |
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13-Dec-2011 |
Nathan Binkert <nate@binkert.org> |
gcc: fix unused variable warnings from GCC 4.6.1
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8601:af28085882dc |
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23-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
SE: move page allocation from PageTable to Process
PageTable supported an allocate() call that called back through the Process to allocate memory, but did not have a method to map addresses without allocating new pages. It makes more sense for Process to do the allocation, so this method was renamed allocateMem() and moved to Process, and uses a new map() call on PageTable.
The remaining uses of the process pointer in PageTable were only to get the name and the PID, so by passing these in directly in the constructor, we can make PageTable completely independent of Process.
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8600:b0d7c64ada19 |
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23-Oct-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
syscall_emul: implement MAP_FIXED option to mmap()
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8232:b28d06a175be |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
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8229:78bf55f23338 |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes
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7678:f19b6a3a8cec |
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13-Sep-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
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6820:2980bd04e6df |
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20-Jan-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
util: do checkpoint aggregation more cleanly, fix last changeset. 1) Move alpha-specific code out of page_table.cc:serialize(). 2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up. 3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN. 4) Fix the memory unserialize that I forgot somehow in the last changeset. 5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py. Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.
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6818:5a0e3a283826 |
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18-Jan-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
util: make a generic checkpoint aggregator that can aggregate different cpts into one multi-programmed cpt. Make minor changes to serialization/unserialization to get it to work properly. Note that checkpoints were made with a comment at the beginning with // - this must be changed to ## to work properly with the python config parser in the aggregator.
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6658:f4de76601762 |
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23-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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6227:a17798f2a52c |
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05-Jun-2009 |
Nathan Binkert <nate@binkert.org> |
types: clean up types, especially signed vs unsigned
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5877:9fe574944f31 |
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16-Feb-2009 |
Lisa Hsu <hsul@eecs.umich.edu> |
sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though.
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5248:b27aab7165da |
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14-Nov-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once.
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5184:8782de2949e5 |
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25-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
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5183:b4decf133fe4 |
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25-Oct-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore.
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5004:7d94cedab264 |
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26-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Address translation: Make the page table more flexible. The page table now stores actual page table entries. It is still a templated class here, but this will be corrected in the near future.
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4762:c94e103c83ad |
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24-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way.
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4521:0236d1cdb330 |
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05-Jun-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Clean up some of vincent's code and commit it Makes page table cache scheme actually work
src/mem/page_table.cc: src/mem/page_table.hh: fix caching scheme to actually work and improve performance
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4183:3d19c1d46946 |
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07-Mar-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.
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3347:c182ee45f6b4 |
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20-Oct-2006 |
Nathan Binkert <binkertn@umich.edu> |
initialize end, clean up loop
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3320:a8910dbabb44 |
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18-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
need some initializations before doing the loop.
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3311:7eb47a60dbd4 |
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17-Oct-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add code to serialize se structures. Lisa is working on the python side of things and will test
src/mem/page_table.cc: src/mem/page_table.hh: add code to serialize/unserialize page table src/sim/process.cc: src/sim/process.hh: add code to serialize/unserialize process
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2979:88f767122b58 |
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14-Aug-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Changed the size parameter from int to int64_t
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2809:9cb5fba079ed |
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27-Jun-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
change the page table from map to hash_map and create small cache to to speed up lookups
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2800:18a615ca6e19 |
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26-Jun-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add syscall emulation page table fault so we can allocate more stack pages
src/cpu/simple/base.cc: add syscall emulation page table fault so we can allocate more stack pages FaultBase::invoke will do this, we don't need to do it here src/sim/faults.hh: I have no idea why this #if was there... gone src/sim/process.cc: make stack_min actually be the current minimum
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2665:a124942bacb8 |
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31-May-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Updated Authors from bk prs info
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2632:1bb2f91485ea |
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22-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
New directory structure: - simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions.
SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure.
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