page_table.cc revision 5183:b4decf133fe4 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Ron Dreslinski
30 *          Ali Saidi
31 */
32
33/**
34 * @file
35 * Definitions of page table.
36 */
37#include <string>
38#include <map>
39#include <fstream>
40
41#include "arch/faults.hh"
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "mem/page_table.hh"
46#include "sim/sim_object.hh"
47#include "sim/system.hh"
48
49using namespace std;
50using namespace TheISA;
51
52PageTable::PageTable(System *_system, Addr _pageSize)
53    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
54      system(_system)
55{
56    assert(isPowerOf2(pageSize));
57    pTableCache[0].vaddr = 0;
58    pTableCache[1].vaddr = 0;
59    pTableCache[2].vaddr = 0;
60}
61
62PageTable::~PageTable()
63{
64}
65
66void
67PageTable::allocate(Addr vaddr, int64_t size)
68{
69    // starting address must be page aligned
70    assert(pageOffset(vaddr) == 0);
71
72    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
73
74    for (; size > 0; size -= pageSize, vaddr += pageSize) {
75        PTableItr iter = pTable.find(vaddr);
76
77        if (iter != pTable.end()) {
78            // already mapped
79            fatal("PageTable::allocate: address 0x%x already mapped",
80                    vaddr);
81        }
82
83        pTable[vaddr] = TheISA::TlbEntry(system->new_page());
84        updateCache(vaddr, pTable[vaddr]);
85    }
86}
87
88bool
89PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
90{
91    Addr page_addr = pageAlign(vaddr);
92
93    if (pTableCache[0].vaddr == page_addr) {
94        entry = pTableCache[0].entry;
95        return true;
96    }
97    if (pTableCache[1].vaddr == page_addr) {
98        entry = pTableCache[1].entry;
99        return true;
100    }
101    if (pTableCache[2].vaddr == page_addr) {
102        entry = pTableCache[2].entry;
103        return true;
104    }
105
106    PTableItr iter = pTable.find(page_addr);
107
108    if (iter == pTable.end()) {
109        return false;
110    }
111
112    updateCache(page_addr, iter->second);
113    entry = iter->second;
114    return true;
115}
116
117bool
118PageTable::translate(Addr vaddr, Addr &paddr)
119{
120    TheISA::TlbEntry entry;
121    if (!lookup(vaddr, entry)) {
122        DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
123        return false;
124    }
125    paddr = pageOffset(vaddr) + entry.pageStart;
126    DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
127    return true;
128}
129
130Fault
131PageTable::translate(RequestPtr req)
132{
133    Addr paddr;
134    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
135           == pageAlign(req->getVaddr()));
136    if (!translate(req->getVaddr(), paddr)) {
137        return Fault(new GenericPageTableFault(req->getVaddr()));
138    }
139    req->setPaddr(paddr);
140    if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
141        panic("Request spans page boundaries!\n");
142        return NoFault;
143    }
144    return NoFault;
145}
146
147void
148PageTable::serialize(std::ostream &os)
149{
150    paramOut(os, "ptable.size", pTable.size());
151
152    int count = 0;
153
154    PTableItr iter = pTable.begin();
155    PTableItr end = pTable.end();
156    while (iter != end) {
157        os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
158
159        paramOut(os, "vaddr", iter->first);
160        iter->second.serialize(os);
161
162        ++iter;
163        ++count;
164    }
165    assert(count == pTable.size());
166}
167
168void
169PageTable::unserialize(Checkpoint *cp, const std::string &section)
170{
171    int i = 0, count;
172    paramIn(cp, section, "ptable.size", count);
173    Addr vaddr;
174    TheISA::TlbEntry *entry;
175
176    pTable.clear();
177
178    while(i < count) {
179        paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
180        entry = new TheISA::TlbEntry();
181        entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
182        pTable[vaddr] = *entry;
183        ++i;
184   }
185}
186
187