page_table.cc revision 10905:a6ca6831e775 
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2003 The Regents of The University of Michigan
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 *          Ron Dreslinski
31 *          Ali Saidi
32 */
33
34/**
35 * @file
36 * Definitions of functional page table.
37 */
38#include <fstream>
39#include <map>
40#include <memory>
41#include <string>
42
43#include "base/bitfield.hh"
44#include "base/intmath.hh"
45#include "base/trace.hh"
46#include "config/the_isa.hh"
47#include "debug/MMU.hh"
48#include "mem/page_table.hh"
49#include "sim/faults.hh"
50#include "sim/sim_object.hh"
51
52using namespace std;
53using namespace TheISA;
54
55FuncPageTable::FuncPageTable(const std::string &__name,
56                             uint64_t _pid, Addr _pageSize)
57        : PageTableBase(__name, _pid, _pageSize)
58{
59}
60
61FuncPageTable::~FuncPageTable()
62{
63}
64
65void
66FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags)
67{
68    bool clobber = flags & Clobber;
69    // starting address must be page aligned
70    assert(pageOffset(vaddr) == 0);
71
72    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
73
74    for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
75        if (!clobber && (pTable.find(vaddr) != pTable.end())) {
76            // already mapped
77            fatal("FuncPageTable::allocate: addr 0x%x already mapped", vaddr);
78        }
79
80        pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr,
81                                         flags & Uncacheable,
82                                         flags & ReadOnly);
83        eraseCacheEntry(vaddr);
84        updateCache(vaddr, pTable[vaddr]);
85    }
86}
87
88void
89FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
90{
91    assert(pageOffset(vaddr) == 0);
92    assert(pageOffset(new_vaddr) == 0);
93
94    DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
95            new_vaddr, size);
96
97    for (; size > 0;
98         size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
99    {
100        assert(pTable.find(vaddr) != pTable.end());
101
102        pTable[new_vaddr] = pTable[vaddr];
103        pTable.erase(vaddr);
104        eraseCacheEntry(vaddr);
105        pTable[new_vaddr].updateVaddr(new_vaddr);
106        updateCache(new_vaddr, pTable[new_vaddr]);
107    }
108}
109
110void
111FuncPageTable::unmap(Addr vaddr, int64_t size)
112{
113    assert(pageOffset(vaddr) == 0);
114
115    DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
116
117    for (; size > 0; size -= pageSize, vaddr += pageSize) {
118        assert(pTable.find(vaddr) != pTable.end());
119        pTable.erase(vaddr);
120        eraseCacheEntry(vaddr);
121    }
122
123}
124
125bool
126FuncPageTable::isUnmapped(Addr vaddr, int64_t size)
127{
128    // starting address must be page aligned
129    assert(pageOffset(vaddr) == 0);
130
131    for (; size > 0; size -= pageSize, vaddr += pageSize) {
132        if (pTable.find(vaddr) != pTable.end()) {
133            return false;
134        }
135    }
136
137    return true;
138}
139
140bool
141FuncPageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
142{
143    Addr page_addr = pageAlign(vaddr);
144
145    if (pTableCache[0].valid && pTableCache[0].vaddr == page_addr) {
146        entry = pTableCache[0].entry;
147        return true;
148    }
149    if (pTableCache[1].valid && pTableCache[1].vaddr == page_addr) {
150        entry = pTableCache[1].entry;
151        return true;
152    }
153    if (pTableCache[2].valid && pTableCache[2].vaddr == page_addr) {
154        entry = pTableCache[2].entry;
155        return true;
156    }
157
158    PTableItr iter = pTable.find(page_addr);
159
160    if (iter == pTable.end()) {
161        return false;
162    }
163
164    updateCache(page_addr, iter->second);
165    entry = iter->second;
166    return true;
167}
168
169bool
170PageTableBase::translate(Addr vaddr, Addr &paddr)
171{
172    TheISA::TlbEntry entry;
173    if (!lookup(vaddr, entry)) {
174        DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
175        return false;
176    }
177    paddr = pageOffset(vaddr) + entry.pageStart();
178    DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
179    return true;
180}
181
182Fault
183PageTableBase::translate(RequestPtr req)
184{
185    Addr paddr;
186    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
187           == pageAlign(req->getVaddr()));
188    if (!translate(req->getVaddr(), paddr)) {
189        return Fault(new GenericPageTableFault(req->getVaddr()));
190    }
191    req->setPaddr(paddr);
192    if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
193        panic("Request spans page boundaries!\n");
194        return NoFault;
195    }
196    return NoFault;
197}
198
199void
200FuncPageTable::serialize(CheckpointOut &cp) const
201{
202    paramOut(cp, "ptable.size", pTable.size());
203
204    PTable::size_type count = 0;
205    for (auto &pte : pTable) {
206        ScopedCheckpointSection sec(cp, csprintf("Entry%d", count++));
207
208        paramOut(cp, "vaddr", pte.first);
209        pte.second.serialize(cp);
210    }
211    assert(count == pTable.size());
212}
213
214void
215FuncPageTable::unserialize(CheckpointIn &cp)
216{
217    int count;
218    paramIn(cp, "ptable.size", count);
219
220    for (int i = 0; i < count; ++i) {
221        ScopedCheckpointSection sec(cp, csprintf("Entry%d", i));
222
223        std::unique_ptr<TheISA::TlbEntry> entry;
224        Addr vaddr;
225
226        paramIn(cp, "vaddr", vaddr);
227        entry.reset(new TheISA::TlbEntry());
228        entry->unserialize(cp);
229
230        pTable[vaddr] = *entry;
231    }
232}
233
234