page_table.cc revision 10558:426665ec11a9 
1/*
2 * Copyright (c) 2014 Advanced Micro Devices, Inc.
3 * Copyright (c) 2003 The Regents of The University of Michigan
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Steve Reinhardt
30 *          Ron Dreslinski
31 *          Ali Saidi
32 */
33
34/**
35 * @file
36 * Definitions of functional page table.
37 */
38#include <fstream>
39#include <map>
40#include <string>
41
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "config/the_isa.hh"
46#include "debug/MMU.hh"
47#include "mem/page_table.hh"
48#include "sim/faults.hh"
49#include "sim/sim_object.hh"
50
51using namespace std;
52using namespace TheISA;
53
54FuncPageTable::FuncPageTable(const std::string &__name,
55                             uint64_t _pid, Addr _pageSize)
56        : PageTableBase(__name, _pid, _pageSize)
57{
58}
59
60FuncPageTable::~FuncPageTable()
61{
62}
63
64void
65FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, uint64_t flags)
66{
67    bool clobber = flags & Clobber;
68    // starting address must be page aligned
69    assert(pageOffset(vaddr) == 0);
70
71    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
72
73    for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
74        if (!clobber && (pTable.find(vaddr) != pTable.end())) {
75            // already mapped
76            fatal("FuncPageTable::allocate: addr 0x%x already mapped", vaddr);
77        }
78
79        pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr,
80                                         flags & Uncacheable,
81                                         flags & ReadOnly);
82        eraseCacheEntry(vaddr);
83        updateCache(vaddr, pTable[vaddr]);
84    }
85}
86
87void
88FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
89{
90    assert(pageOffset(vaddr) == 0);
91    assert(pageOffset(new_vaddr) == 0);
92
93    DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
94            new_vaddr, size);
95
96    for (; size > 0;
97         size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
98    {
99        assert(pTable.find(vaddr) != pTable.end());
100
101        pTable[new_vaddr] = pTable[vaddr];
102        pTable.erase(vaddr);
103        eraseCacheEntry(vaddr);
104        pTable[new_vaddr].updateVaddr(new_vaddr);
105        updateCache(new_vaddr, pTable[new_vaddr]);
106    }
107}
108
109void
110FuncPageTable::unmap(Addr vaddr, int64_t size)
111{
112    assert(pageOffset(vaddr) == 0);
113
114    DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size);
115
116    for (; size > 0; size -= pageSize, vaddr += pageSize) {
117        assert(pTable.find(vaddr) != pTable.end());
118        pTable.erase(vaddr);
119        eraseCacheEntry(vaddr);
120    }
121
122}
123
124bool
125FuncPageTable::isUnmapped(Addr vaddr, int64_t size)
126{
127    // starting address must be page aligned
128    assert(pageOffset(vaddr) == 0);
129
130    for (; size > 0; size -= pageSize, vaddr += pageSize) {
131        if (pTable.find(vaddr) != pTable.end()) {
132            return false;
133        }
134    }
135
136    return true;
137}
138
139bool
140FuncPageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
141{
142    Addr page_addr = pageAlign(vaddr);
143
144    if (pTableCache[0].valid && pTableCache[0].vaddr == page_addr) {
145        entry = pTableCache[0].entry;
146        return true;
147    }
148    if (pTableCache[1].valid && pTableCache[1].vaddr == page_addr) {
149        entry = pTableCache[1].entry;
150        return true;
151    }
152    if (pTableCache[2].valid && pTableCache[2].vaddr == page_addr) {
153        entry = pTableCache[2].entry;
154        return true;
155    }
156
157    PTableItr iter = pTable.find(page_addr);
158
159    if (iter == pTable.end()) {
160        return false;
161    }
162
163    updateCache(page_addr, iter->second);
164    entry = iter->second;
165    return true;
166}
167
168bool
169PageTableBase::translate(Addr vaddr, Addr &paddr)
170{
171    TheISA::TlbEntry entry;
172    if (!lookup(vaddr, entry)) {
173        DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
174        return false;
175    }
176    paddr = pageOffset(vaddr) + entry.pageStart();
177    DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
178    return true;
179}
180
181Fault
182PageTableBase::translate(RequestPtr req)
183{
184    Addr paddr;
185    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
186           == pageAlign(req->getVaddr()));
187    if (!translate(req->getVaddr(), paddr)) {
188        return Fault(new GenericPageTableFault(req->getVaddr()));
189    }
190    req->setPaddr(paddr);
191    if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
192        panic("Request spans page boundaries!\n");
193        return NoFault;
194    }
195    return NoFault;
196}
197
198void
199FuncPageTable::serialize(std::ostream &os)
200{
201    paramOut(os, "ptable.size", pTable.size());
202
203    PTable::size_type count = 0;
204
205    PTableItr iter = pTable.begin();
206    PTableItr end = pTable.end();
207    while (iter != end) {
208        os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
209
210        paramOut(os, "vaddr", iter->first);
211        iter->second.serialize(os);
212
213        ++iter;
214        ++count;
215    }
216    assert(count == pTable.size());
217}
218
219void
220FuncPageTable::unserialize(Checkpoint *cp, const std::string &section)
221{
222    int i = 0, count;
223    paramIn(cp, section, "ptable.size", count);
224
225    pTable.clear();
226
227    while (i < count) {
228        TheISA::TlbEntry *entry;
229        Addr vaddr;
230
231        paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
232        entry = new TheISA::TlbEntry();
233        entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
234        pTable[vaddr] = *entry;
235        delete entry;
236        ++i;
237    }
238}
239
240