page_table.cc revision 4183:3d19c1d46946
13006SN/A/* 23006SN/A * Copyright (c) 2003 The Regents of The University of Michigan 34398SN/A * All rights reserved. 411390Ssteve.reinhardt@amd.com * 511390Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 68540SN/A * modification, are permitted provided that the following conditions are 711687Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 811687Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 911687Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 1011687Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1111687Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 1211390Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 1311390Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 1410036SAli.Saidi@ARM.com * this software without specific prior written permission. 1510036SAli.Saidi@ARM.com * 1611530Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711390Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811390Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911390Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011390Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111390Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210488Snilay@cs.wisc.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310488Snilay@cs.wisc.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411390Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511390Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611390Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710488Snilay@cs.wisc.edu * 2810488Snilay@cs.wisc.edu * Authors: Steve Reinhardt 2911390Ssteve.reinhardt@amd.com * Ron Dreslinski 3011390Ssteve.reinhardt@amd.com * Ali Saidi 3111390Ssteve.reinhardt@amd.com */ 3211390Ssteve.reinhardt@amd.com 3311390Ssteve.reinhardt@amd.com/** 3411390Ssteve.reinhardt@amd.com * @file 3511390Ssteve.reinhardt@amd.com * Definitions of page table. 3611390Ssteve.reinhardt@amd.com */ 3711390Ssteve.reinhardt@amd.com#include <string> 3811390Ssteve.reinhardt@amd.com#include <map> 3911530Sandreas.sandberg@arm.com#include <fstream> 4010036SAli.Saidi@ARM.com 418540SN/A#include "arch/faults.hh" 428540SN/A#include "base/bitfield.hh" 438540SN/A#include "base/intmath.hh" 448540SN/A#include "base/trace.hh" 458540SN/A#include "mem/page_table.hh" 468540SN/A#include "sim/builder.hh" 475510SN/A#include "sim/sim_object.hh" 485510SN/A#include "sim/system.hh" 498540SN/A 508540SN/Ausing namespace std; 518540SN/Ausing namespace TheISA; 528540SN/A 538540SN/APageTable::PageTable(System *_system, Addr _pageSize) 548540SN/A : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))), 558540SN/A system(_system) 565510SN/A{ 575510SN/A assert(isPowerOf2(pageSize)); 588540SN/A pTableCache[0].vaddr = 0; 5911955Sgabeblack@google.com pTableCache[1].vaddr = 0; 6011530Sandreas.sandberg@arm.com pTableCache[2].vaddr = 0; 6111390Ssteve.reinhardt@amd.com} 628540SN/A 637935SN/APageTable::~PageTable() 6411390Ssteve.reinhardt@amd.com{ 6511390Ssteve.reinhardt@amd.com} 6611390Ssteve.reinhardt@amd.com 678540SN/AFault 6811390Ssteve.reinhardt@amd.comPageTable::page_check(Addr addr, int64_t size) const 6911390Ssteve.reinhardt@amd.com{ 7011390Ssteve.reinhardt@amd.com if (size < sizeof(uint64_t)) { 717935SN/A if (!isPowerOf2(size)) { 7211390Ssteve.reinhardt@amd.com panic("Invalid request size!\n"); 7311390Ssteve.reinhardt@amd.com return genMachineCheckFault(); 747935SN/A } 757935SN/A 7611390Ssteve.reinhardt@amd.com if ((size - 1) & addr) 7711390Ssteve.reinhardt@amd.com return genAlignmentFault(); 7810488Snilay@cs.wisc.edu } 797935SN/A else { 8011390Ssteve.reinhardt@amd.com if ((addr & (VMPageSize - 1)) + size > VMPageSize) { 818540SN/A panic("Invalid request size!\n"); 828540SN/A return genMachineCheckFault(); 8311390Ssteve.reinhardt@amd.com } 8411390Ssteve.reinhardt@amd.com 8511390Ssteve.reinhardt@amd.com if ((sizeof(uint64_t) - 1) & addr) 8611390Ssteve.reinhardt@amd.com return genAlignmentFault(); 8711390Ssteve.reinhardt@amd.com } 8811390Ssteve.reinhardt@amd.com 8911390Ssteve.reinhardt@amd.com return NoFault; 9011390Ssteve.reinhardt@amd.com} 9111390Ssteve.reinhardt@amd.com 9211687Sandreas.hansson@arm.com 9311390Ssteve.reinhardt@amd.com 9411687Sandreas.hansson@arm.com 9511390Ssteve.reinhardt@amd.comvoid 9611390Ssteve.reinhardt@amd.comPageTable::allocate(Addr vaddr, int64_t size) 9711390Ssteve.reinhardt@amd.com{ 9811390Ssteve.reinhardt@amd.com // starting address must be page aligned 9911390Ssteve.reinhardt@amd.com assert(pageOffset(vaddr) == 0); 10011390Ssteve.reinhardt@amd.com 10111390Ssteve.reinhardt@amd.com DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); 10211390Ssteve.reinhardt@amd.com 10311390Ssteve.reinhardt@amd.com for (; size > 0; size -= pageSize, vaddr += pageSize) { 10411390Ssteve.reinhardt@amd.com m5::hash_map<Addr,Addr>::iterator iter = pTable.find(vaddr); 10511390Ssteve.reinhardt@amd.com 10611390Ssteve.reinhardt@amd.com if (iter != pTable.end()) { 10711390Ssteve.reinhardt@amd.com // already mapped 10811390Ssteve.reinhardt@amd.com fatal("PageTable::allocate: address 0x%x already mapped", vaddr); 10911390Ssteve.reinhardt@amd.com } 11011390Ssteve.reinhardt@amd.com 11111390Ssteve.reinhardt@amd.com pTable[vaddr] = system->new_page(); 11211390Ssteve.reinhardt@amd.com pTableCache[2].paddr = pTableCache[1].paddr; 11311390Ssteve.reinhardt@amd.com pTableCache[2].vaddr = pTableCache[1].vaddr; 11411390Ssteve.reinhardt@amd.com pTableCache[1].paddr = pTableCache[0].paddr; 11511390Ssteve.reinhardt@amd.com pTableCache[1].vaddr = pTableCache[0].vaddr; 11611390Ssteve.reinhardt@amd.com pTableCache[0].paddr = pTable[vaddr]; 11711390Ssteve.reinhardt@amd.com pTableCache[0].vaddr = vaddr; 11811687Sandreas.hansson@arm.com } 11911687Sandreas.hansson@arm.com} 12010220Sandreas.hansson@arm.com 12110220Sandreas.hansson@arm.com 12211390Ssteve.reinhardt@amd.com 12311606Sandreas.sandberg@arm.combool 12411606Sandreas.sandberg@arm.comPageTable::translate(Addr vaddr, Addr &paddr) 12511606Sandreas.sandberg@arm.com{ 12611606Sandreas.sandberg@arm.com Addr page_addr = pageAlign(vaddr); 12711606Sandreas.sandberg@arm.com paddr = 0; 12811606Sandreas.sandberg@arm.com 12911530Sandreas.sandberg@arm.com if (pTableCache[0].vaddr == vaddr) { 13011390Ssteve.reinhardt@amd.com paddr = pTableCache[0].paddr; 13111390Ssteve.reinhardt@amd.com return true; 13211268Satgutier@umich.edu } 13311268Satgutier@umich.edu if (pTableCache[1].vaddr == vaddr) { 13411390Ssteve.reinhardt@amd.com paddr = pTableCache[1].paddr; 13511390Ssteve.reinhardt@amd.com return true; 13611390Ssteve.reinhardt@amd.com } 13711390Ssteve.reinhardt@amd.com if (pTableCache[2].vaddr == vaddr) { 13811390Ssteve.reinhardt@amd.com paddr = pTableCache[2].paddr; 13911390Ssteve.reinhardt@amd.com return true; 14011268Satgutier@umich.edu } 14111570SCurtis.Dunham@arm.com 14211390Ssteve.reinhardt@amd.com m5::hash_map<Addr,Addr>::iterator iter = pTable.find(page_addr); 14311606Sandreas.sandberg@arm.com 14411606Sandreas.sandberg@arm.com if (iter == pTable.end()) { 14511268Satgutier@umich.edu return false; 14611606Sandreas.sandberg@arm.com } 14711606Sandreas.sandberg@arm.com 14811268Satgutier@umich.edu paddr = iter->second + pageOffset(vaddr); 14911268Satgutier@umich.edu return true; 15011606Sandreas.sandberg@arm.com} 15111390Ssteve.reinhardt@amd.com 1523006SN/A 1533006SN/AFault 154PageTable::translate(RequestPtr &req) 155{ 156 Addr paddr; 157 assert(pageAlign(req->getVaddr() + req->getSize() - 1) 158 == pageAlign(req->getVaddr())); 159 if (!translate(req->getVaddr(), paddr)) { 160 return Fault(new PageTableFault(req->getVaddr())); 161 } 162 req->setPaddr(paddr); 163 return page_check(req->getPaddr(), req->getSize()); 164} 165 166void 167PageTable::serialize(std::ostream &os) 168{ 169 paramOut(os, "ptable.size", pTable.size()); 170 171 int count = 0; 172 173 m5::hash_map<Addr,Addr>::iterator iter = pTable.begin(); 174 m5::hash_map<Addr,Addr>::iterator end = pTable.end(); 175 while (iter != end) { 176 paramOut(os, csprintf("ptable.entry%dvaddr", count), iter->first); 177 paramOut(os, csprintf("ptable.entry%dpaddr", count), iter->second); 178 179 ++iter; 180 ++count; 181 } 182 assert(count == pTable.size()); 183} 184 185void 186PageTable::unserialize(Checkpoint *cp, const std::string §ion) 187{ 188 int i = 0, count; 189 paramIn(cp, section, "ptable.size", count); 190 Addr vaddr, paddr; 191 192 pTable.clear(); 193 194 while(i < count) { 195 paramIn(cp, section, csprintf("ptable.entry%dvaddr", i), vaddr); 196 paramIn(cp, section, csprintf("ptable.entry%dpaddr", i), paddr); 197 pTable[vaddr] = paddr; 198 ++i; 199 } 200 201} 202 203