page_table.cc revision 5184:8782de2949e5 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Ron Dreslinski
30 *          Ali Saidi
31 */
32
33/**
34 * @file
35 * Definitions of page table.
36 */
37#include <string>
38#include <map>
39#include <fstream>
40
41#include "arch/faults.hh"
42#include "base/bitfield.hh"
43#include "base/intmath.hh"
44#include "base/trace.hh"
45#include "mem/page_table.hh"
46#include "sim/process.hh"
47#include "sim/sim_object.hh"
48#include "sim/system.hh"
49
50using namespace std;
51using namespace TheISA;
52
53PageTable::PageTable(Process *_process, Addr _pageSize)
54    : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
55      process(_process)
56{
57    assert(isPowerOf2(pageSize));
58    pTableCache[0].vaddr = 0;
59    pTableCache[1].vaddr = 0;
60    pTableCache[2].vaddr = 0;
61}
62
63PageTable::~PageTable()
64{
65}
66
67void
68PageTable::allocate(Addr vaddr, int64_t size)
69{
70    // starting address must be page aligned
71    assert(pageOffset(vaddr) == 0);
72
73    DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size);
74
75    for (; size > 0; size -= pageSize, vaddr += pageSize) {
76        PTableItr iter = pTable.find(vaddr);
77
78        if (iter != pTable.end()) {
79            // already mapped
80            fatal("PageTable::allocate: address 0x%x already mapped",
81                    vaddr);
82        }
83
84        pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
85                process->system->new_page());
86        updateCache(vaddr, pTable[vaddr]);
87    }
88}
89
90bool
91PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry)
92{
93    Addr page_addr = pageAlign(vaddr);
94
95    if (pTableCache[0].vaddr == page_addr) {
96        entry = pTableCache[0].entry;
97        return true;
98    }
99    if (pTableCache[1].vaddr == page_addr) {
100        entry = pTableCache[1].entry;
101        return true;
102    }
103    if (pTableCache[2].vaddr == page_addr) {
104        entry = pTableCache[2].entry;
105        return true;
106    }
107
108    PTableItr iter = pTable.find(page_addr);
109
110    if (iter == pTable.end()) {
111        return false;
112    }
113
114    updateCache(page_addr, iter->second);
115    entry = iter->second;
116    return true;
117}
118
119bool
120PageTable::translate(Addr vaddr, Addr &paddr)
121{
122    TheISA::TlbEntry entry;
123    if (!lookup(vaddr, entry)) {
124        DPRINTF(MMU, "Couldn't Translate: %#x\n", vaddr);
125        return false;
126    }
127    paddr = pageOffset(vaddr) + entry.pageStart();
128    DPRINTF(MMU, "Translating: %#x->%#x\n", vaddr, paddr);
129    return true;
130}
131
132Fault
133PageTable::translate(RequestPtr req)
134{
135    Addr paddr;
136    assert(pageAlign(req->getVaddr() + req->getSize() - 1)
137           == pageAlign(req->getVaddr()));
138    if (!translate(req->getVaddr(), paddr)) {
139        return Fault(new GenericPageTableFault(req->getVaddr()));
140    }
141    req->setPaddr(paddr);
142    if ((paddr & (pageSize - 1)) + req->getSize() > pageSize) {
143        panic("Request spans page boundaries!\n");
144        return NoFault;
145    }
146    return NoFault;
147}
148
149void
150PageTable::serialize(std::ostream &os)
151{
152    paramOut(os, "ptable.size", pTable.size());
153
154    int count = 0;
155
156    PTableItr iter = pTable.begin();
157    PTableItr end = pTable.end();
158    while (iter != end) {
159        os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n";
160
161        paramOut(os, "vaddr", iter->first);
162        iter->second.serialize(os);
163
164        ++iter;
165        ++count;
166    }
167    assert(count == pTable.size());
168}
169
170void
171PageTable::unserialize(Checkpoint *cp, const std::string &section)
172{
173    int i = 0, count;
174    paramIn(cp, section, "ptable.size", count);
175    Addr vaddr;
176    TheISA::TlbEntry *entry;
177
178    pTable.clear();
179
180    while(i < count) {
181        paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr);
182        entry = new TheISA::TlbEntry();
183        entry->unserialize(cp, csprintf("%s.Entry%d", name(), i));
184        pTable[vaddr] = *entry;
185        ++i;
186   }
187}
188
189