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13958:1945df12e5b0 |
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07-Jan-2019 |
Jairo Balart <jairo.balart@metempsy.com> |
config: add an option to list and select indirect branch predictor
Change-Id: I9a855d36de7d95b7785ff8a897899037cea6a3d8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/15320 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13864:815193aa6617 |
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22-Apr-2019 |
Po-Hao Su <supohaosu@gmail.com> |
configs: Use param to get number of processors
Although the parameter np is the same as options.num_cpus. But we should get the number of processors from the parameters of the function.
Change-Id: I3eb02d7c75ab35410b773b06001d1b145cdccd49 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18248 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
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13803:32c104f40e57 |
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25-Jul-2018 |
Daniel R. Carvalho <odanrc@yahoo.com.br> |
configs: Remove default kernel value from system creation
Kernel was being set using a placeholder and then assigned the correct value. This would generate the following error if the placeholder file did not exist: 'IOError: Can't find file <placeholder> on path'
This patch follows the same directions of commit 12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default values, forcing the user to properly configure the kernel.
Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13774:a1be2a0c55f2 |
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25-Feb-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
configs: Use absolute import paths
Use absoluate import paths to be Python 3 compatible. This also imports absolute_import from __future__ to ensure that Python 2.7 behaves the same way as Python 3.
Change-Id: Ica06ed95814e9cd3e768b3e1785075e36f6e56d0 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16708 Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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13731:67cd980cb20f |
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26-Jan-2019 |
Andreas Sandberg <andreas.sandberg@arm.com> |
configs: Fix Python 3 iterator and exec compatibility issues
Python 2.7 used to return lists for operations such as map and range, this has changed in Python 3. To make the configs Python 3 compliant, add explicit conversions from iterators to lists where needed, replace xrange with range, and fix changes to exec syntax.
This change doesn't fix import paths since that might require us to restructure the configs slightly.
Change-Id: Idcea8482b286779fc98b4e144ca8f54069c08024 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/16002 Reviewed-by: Gabe Black <gabeblack@google.com>
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13684:076506a21535 |
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24-Jan-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
configs: simpoint-profile usable with NonCachingCPUs only
NonCachingCPU is replacing the Atomic+fastmem option.
Change-Id: I66f5c8a880d1b3fd1331871d89e8d6a229938e57 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15935 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13608:e91969b61d3d |
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25-Jan-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm, configs: Create single instance of DTB autogeneration
This patch is rewriting the DTB autogeneration functions available in fs_bigLITTLE.py and fs.py as a single method in the GenericArmSystem so that other configuration scripts can make use of it.
Change-Id: I492bbf77e6b0ac5c5fbdbc75c0eecba29bd63bda Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15958 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13606:2ad4449e6cb4 |
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24-Jan-2019 |
Ciro Santilli <ciro.santilli@arm.com> |
configs: fs.py remove --generate-dtb and enable it by default
The option is now enabled if neither --bare-metal nor --dtb-filename are given.
This is what fs_bigLITTLE.py already did before this patch.
Change-Id: I9179f8c9fa18edbd1e0f1a65ea2c1de0a26b7921 Reviewed-on: https://gem5-review.googlesource.com/c/15899 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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13432:6ce67b7e6e44 |
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07-Nov-2018 |
Pau Cabre <pau.cabre@metempsy.com> |
configs: Added an option for choosing branch predictor type
Added the parameter "--bp-type" to set the branch predictor type Added the parameter "--list-bp-types" to list all the available branch predictor types
Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14015 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13012:5fbc6b9c64bc |
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15-Mar-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
cpu: Replace the fastmem with a new CPU model
The AtomicSimpleCPU used to be able to access memory directly to speed up simulation if no caches are used. This is fine as long as no switching between CPU models is required. In order to switch to a new CPU model that requires caches, we currently need to checkpoint the system and restore it into a new configuration. The new 'atomic_noncaching' memory mode provides a solution that avoids this issue since caches are bypassed in this mode. This changeset removes the old fastmem option from the AtomicSimpleCPU and introduces a new CPU, NonCachingSimpleCPU, which derives from the AtomicSimpleCPU.
The NonCachingSimpleCPU uses the same mechanism as the AtomicSimpleCPU used to use when accessing memory in when fastmem was enabled.
This changeset also introduces a new switcheroo test that tests switching between a NonCachingSimpleCPU and a TimingSimpleCPU with caches.
Change-Id: If01893f9b37528b14f530c11ce6f53c097582c21 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12419 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12941:24771c7aee2e |
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28-Aug-2018 |
Andreas Sandberg <andreas.sandberg@arm.com> |
config: Move KVM CPU checking to CpuConfig helper module
Both se.py and fs.py need to check if a CPU is a KVM CPU. This is somewhat involved since CPUs can be disabled at compile time. Enable better code reuse by moving it to the CpuConfig module.
Change-Id: I47b1512ecb62e757399a407a0e41be83b9f83be3 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12418 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12598:b80b2d9a251b |
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12-Feb-2018 |
Nikos Nikoleris <nikos.nikoleris@arm.com> |
arch-arm, configs: Treat the bootloader rom as cacheable memory
Prior to this changeset the bootloader rom (instantiated as a SimpleMemory) in ruby Arm systems was treated as an IO device and it was fronted by a DMA controller. This changeset moves the bootloader rom and adds it to the system as another memory with a dedicated directory controller.
Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8741 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12564:2778478ca882 |
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06-Mar-2018 |
Gabe Black <gabeblack@google.com> |
config: Switch from the print statement to the print function.
Change-Id: I701fa58cfcfa2767ce9ad24da314a053889878d0 Reviewed-on: https://gem5-review.googlesource.com/8762 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
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12490:a98a4a21417a |
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04-Feb-2018 |
Nayan Deshmukh <nayan26deshmukh@gmail.com> |
config: remove dead code in fs.py
We have not added the --generate-dtb option for non-ARM systems and hence this case becomes dead code. It also leads to error on non-ARM systems as is tries to access a non existent field.
Change-Id: Ia926bd0c61efa275bc5e3864b8a9c3ffb7aa3cb5 Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com> Reviewed-on: https://gem5-review.googlesource.com/7801 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12475:c6a23d6370de |
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14-Mar-2016 |
Glenn Bergmans <glenn.bergmans@arm.com> |
config: Embed Device Tree generation in fs.py config
Equips the fs.py config routine with an extra commandline option --generate-dtb that will generate a dtb file automatically before running the simulation. Only works with ARM systems and gives a warning if the simulated system is not of --machine-type VExpress_GEM5_V1.
Change-Id: I7766e5459fd9bec2245de83cef103091ebaf7229 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5968 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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12395:322bb93e5f06 |
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09-Nov-2017 |
Swapnil Haria <swapnilster@gmail.com> |
mem-ruby: Support atomic_noncaching acceses in ruby
Ruby has no support for atomic_noncaching accesses, which prevents using it with kvm-cpu. This patch fixes this by directly forwarding atomic requests from the ruby port/sequencer to the corresponding directory based on the destination address of the packet.
Change-Id: I0b4928bfda44fd9e5e48583c51d1ea422800da2d Reviewed-on: https://gem5-review.googlesource.com/5601 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
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12079:a5cc6df83fcf |
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23-Feb-2017 |
Gedare Bloom <gedare@rtems.org> |
configs, arm: add option to enable security extensions
Change-Id: I0c839bb649a5d2d73080b7e718da3c9b5839cf8c Signed-off-by: Gedare Bloom <gedare@rtems.org> Reviewed-on: https://gem5-review.googlesource.com/3264 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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12014:f973caaf935d |
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08-May-2017 |
Gabe Black <gabeblack@google.com> |
config: Fix up some configs to not use CPU aliases.
Support for CPU aliases were removed recently.
Change-Id: I3c1173dc34170d8639d95e52bf660f248848f77f Reviewed-on: https://gem5-review.googlesource.com/3100 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
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11839:dd6df2e47c14 |
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14-Feb-2017 |
Curtis Dunham <Curtis.Dunham@arm.com> |
sim, kvm: make KvmVM a System parameter
A KVM VM is typically a child of the System object already, but for solving future issues with configuration graph resolution, the most logical way to keep track of this object is for it to be an actual parameter of the System object.
Change-Id: I965ded22203ff8667db9ca02de0042ff1c772220 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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11790:f1ffedcf3b98 |
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09-Jan-2017 |
Matthias Jung <jungma@eit.uni-kl.de> |
config: Fix missing include in fs.py
Bugfix for Elastic Traces
This patch fixes the bug when elastic traces are used:
build/ARM/gem5.opt \ configs/example/fs.py \ --cpu-type=arm_detailed \ --num-cpu=1 \ --mem-type=SimpleMemory \ --mem-size=512MB \ --mem-channels=1 \ --caches \ --elastic-trace-en \ --data-trace-file=data.proto.gz \ --inst-trace-file=inst.proto.gz \ --machine-type=VExpress_EMM \ --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \ --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \ --disk-image=linux-aarch32-ael.img
NameError: global name 'CpuConfig' is not defined
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
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11682:612f75cf36a0 |
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14-Oct-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Make configs/common a Python package
Continue along the same line as the recent patch that made the Ruby-related config scripts Python packages and make also the configs/common directory a package.
All affected config scripts are updated (hopefully).
Note that this change makes it apparent that the current organisation and naming of the config directory and its subdirectories is rather chaotic. We mix scripts that are directly invoked with scripts that merely contain convenience functions. While it is not addressed in this patch we should follow up with a re-organisation of the config structure, and renaming of some of the packages.
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11670:6ce719503eae |
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13-Oct-2016 |
Andreas Hansson <andreas.hansson@arm.com> |
ruby: Fix regressions and make Ruby configs Python packages
This patch moves the addition of network options into the Ruby module to avoid the regressions all having to add it explicitly. Doing this exposes an issue in our current config system though, namely the fact that addtoPath is relative to the Python script being executed. Since both example and regression scripts use the Ruby module we would end up with two different (relative) paths being added. Instead we take a first step at turning the config modules into Python packages, simply by adding a __init__.py in the configs/ruby, configs/topologies and configs/network subdirectories.
As a result, we can now add the top-level configs directory to the Python search path, and then use the package names in the various modules. The example scripts are also updated, and the messy path-deducing variations in the scripts are unified.
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11662:004d34b65092 |
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06-Oct-2016 |
Tushar Krishna <tushar@ece.gatech.edu> |
config: add a separate config file for the network. This patch adds a new file configs/network/Network.py to setup the network, instead of doing that within Ruby.py.
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11598:e0ddee91eb13 |
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10-Aug-2016 |
Andreas Sandberg <andreas.sandberg@arm.com> |
arm, config: Add initial support for Ruby
Add initial support for creating an ARM system with a Ruby-based memory system. This support is currently experimental and limited to the new VExpress_GEM5_V1 platform.
Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
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11291:9d2364203316 |
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07-Jan-2016 |
Gabor Dozsa <gabor.dozsa@arm.com> |
config: Updates for distributed gem5 simulations
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11251:a15c86af004a |
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07-Dec-2015 |
Radhika Jagtap <radhika.jagtap@ARM.com> |
config: Enable elastic trace capture and replay in se/fs
This patch adds changes to the configuration scripts to support elastic tracing and replay.
The patch adds a command line option to enable elastic tracing in SE mode and FS mode. When enabled the Elastic Trace cpu probe is attached to O3CPU and a few O3 CPU parameters are tuned. The Elastic Trace probe writes out both instruction fetch and data dependency traces. The patch also enables configuring the TraceCPU to replay traces using the SE and FS script.
The replay run is designed to resume from checkpoint using atomic cpu to restore state keeping it consistent with FS run flow. It then switches to TraceCPU to replay the input traces.
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11183:276ad9121192 |
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03-Nov-2015 |
Erfan Azarkhish <erfan.azarkhish@unibo.it> |
mem: hmc: top level design
This patch enables modeling a complete Hybrid Memory Cube (HMC) device. It highly reuses the existing components in gem5's general memory system with some small modifications. This changeset requires additional patches to model a complete HMC device.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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11150:a8a64cca231b |
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30-Sep-2015 |
Mitch Hayenga <mitch.hayenga@arm.com> |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
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10780:46070443051e |
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08-Apr-2015 |
Curtis Dunham <Curtis.Dunham@arm.com> |
config: Support full-system with SST's memory system
This patch adds an example configuration in ext/sst/tests/ that allows an SST/gem5 instance to simulate a 4-core AArch64 system with SST's memHierarchy components providing all the caches and memories.
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10747:3fe41011333d |
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19-Mar-2015 |
Chris Emmons <Chris.Emmons@arm.com> |
config: Specify OS type and release on command line
This patch enables users to speficy --os-type on the command line. This option is used to take specific actions for an OS type, such as changing the kernel command line. This patch is part of the Android KitKat enablement.
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10697:71c40e5c8bd4 |
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16-Jan-2015 |
Curtis Dunham <Curtis.Dunham@arm.com> |
config: add --root-device machine parameter
In case /dev/sda1 is not actually the boot partition for an image, we can override it on the command line or in a benchmark definition.
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10635:ab05a080d7c5 |
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03-Jan-2015 |
Anthony Gutierrez <atgutier@umich.edu> |
arm: fix build_drive_system when not using default options
when trying to dual boot on arm build_drive_system will only use the default values for the dtb file, number of processors, and disk image. if you are using the non-default files by passing values on the command line for example, or by making a new entry in Benchmarks.py, the build config scripts will still look for the default files. this will lead to the wrong system files being used, or the simulator will fail if you do not have them.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
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10608:427f988fe6e5 |
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23-Dec-2014 |
Dam Sunwoo <dam.sunwoo@arm.com> |
config: Add options to take/resume from SimPoint checkpoints
More documentation at http://gem5.org/Simpoints
Steps to profile, generate, and use SimPoints with gem5:
1. To profile workload and generate SimPoint BBV file, use the following option:
--simpoint-profile --simpoint-interval <interval length>
Requires single Atomic CPU and fastmem. <interval length> is in number of instructions.
2. Generate SimPoint analysis using SimPoint 3.2 from UCSD. (SimPoint 3.2 not included with this flow.)
3. To take gem5 checkpoints based on SimPoint analysis, use the following option:
--take-simpoint-checkpoint=<simpoint file path>,<weight file path>,<interval length>,<warmup length>
<simpoint file> and <weight file> is generated by SimPoint analysis tool from UCSD. SimPoint 3.2 format expected. <interval length> and <warmup length> are in number of instructions.
4. To resume from gem5 SimPoint checkpoints, use the following option:
--restore-simpoint-checkpoint -r <N> --checkpoint-dir <simpoint checkpoint path>
<N> is (SimPoint index + 1). E.g., "-r 1" will resume from SimPoint #0.
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10594:4fdc929c0aaa |
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04-Dec-2014 |
Gabe Black <gabeblack@google.com> |
config: Add two options for setting the kernel command line.
Both options accept template which will, through python string formatting, have "mem", "disk", and "script" values substituted in from the mdesc. Additional values can be used on a case by case basis by passing them as keyword arguments to the fillInCmdLine function. That makes it possible to have specialized parameters for a particular ISA, for instance.
The first option lets you specify the template directly, and the other lets you specify a file which has the template in it.
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10547:b61dc895269a |
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18-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
configs: small fix to ruby portion of fs.py and se.py In fs.py the io port controller was being attached to the iobus multiple times. This should be done only once. In se.py, the the option use_map was being set which no longer exists.
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10524:fff17530cef6 |
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06-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: interface with classic memory controller This patch is the final in the series. The whole series and this patch in particular were written with the aim of interfacing ruby's directory controller with the memory controller in the classic memory system. This is being done since ruby's memory controller has not being kept up to date with the changes going on in DRAMs. Classic's memory controller is more up to date and supports multiple different types of DRAM. This also brings classic and ruby ever more close. The patch also changes ruby's memory controller to expose the same interface.
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10519:7a3ad4b09ce4 |
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06-Nov-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
ruby: single physical memory in fs mode Both ruby and the system used to maintain memory copies. With the changes carried for programmed io accesses, only one single memory is required for fs simulations. This patch sets the copy of memory that used to reside with the system to null, so that no space is allocated, but address checks can still be carried out. All the memory accesses now source and sink values to the memory maintained by ruby.
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10512:b423e1d0735e |
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30-Oct-2014 |
Ali Saidi <Ali.Saidi@ARM.com> |
arm, tests: Update config files to more recent kernels and create 64-bit regressions.
This changes the default ARM system to a Versatile Express-like system that supports 2GB of memory and PCI devices and updates the default kernels/file-systems for AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some platforms that are no longer supported have been pruned from the configuration files.
In addition a set of 64-bit ARM regressions have been added to the regression system.
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10120:f5ceb3c3edb6 |
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20-Mar-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
config: ruby: rename _cpu_ruby_ports to _cpu_ports
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10119:6f3f839bb496 |
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20-Mar-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
config: fs.py: move creating of test/drive systems to functions The code that creates test and drive systems is being moved to separate functions so as to make the code more readable. Ultimately the two functions would be combined so that the replicated code is eliminated.
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10118:5e1f04b4d5e4 |
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20-Mar-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
config: remove ruby_fs.py
The patch removes the ruby_fs.py file. The functionality is being moved to fs.py. This would being ruby fs simulations in line with how ruby se simulations are started (using --ruby option). The alpha fs config functions are being combined for classing and ruby memory systems. This required renaming the piobus in ruby to iobus. So, we will have stats being renamed in the stats file for ruby fs regression.
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10056:33db5d81c2cb |
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31-Jan-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
config: correct bug in x86 drive sys instantiation
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10041:fae4550d2103 |
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27-Jan-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
config: allow more than 3GB of memory for x86 simulations This patch edits the configuration files so that x86 simulations can have more than 3GB of memory. It also corrects a bug in the MemConfig.py script.
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10037:5cac77888310 |
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24-Jan-2014 |
ARM gem5 Developers |
arm: Add support for ARMv8 (AArch64 & AArch32)
Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 kernel you are restricted to AArch64 user-mode binaries. This will be addressed in a later patch.
Note: Virtualization is only supported in AArch32 mode. This will also be fixed in a later patch.
Contributors: Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation) Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation) Mbou Eyole (AArch64 NEON, validation) Ali Saidi (AArch64 Linux support, code integration, validation) Edmund Grimley-Evans (AArch64 FP) William Wang (AArch64 Linux support) Rene De Jong (AArch64 Linux support, performance opt.) Matt Horsnell (AArch64 MP, validation) Matt Evans (device models, code integration, validation) Chris Adeniyi-Jones (AArch64 syscall-emulation) Prakash Ramrakhyani (validation) Dam Sunwoo (validation) Chander Sudanthi (validation) Stephan Diestelhorst (validation) Andreas Hansson (code integration, performance opt.) Eric Van Hensbergen (performance opt.) Gabe Black
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#
9935:cc9dc514036e |
|
17-Oct-2013 |
Dam Sunwoo <dam.sunwoo@arm.com> |
util: Streamline .apc project convertsion script
This Python script generates an ARM DS-5 Streamline .apc project based on gem5 run. To successfully convert, the gem5 runs needs to be run with the context-switch-based stats dump option enabled (The guest kernel also needs to be patched to allow gem5 interrogate its task information.) See help for more information.
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#
9836:4411b4e0c03a |
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19-Aug-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Command line support for multi-channel memory
This patch adds support for specifying multi-channel memory configurations on the command line, e.g. 'se/fs.py --mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it enhances the functionality of MemConfig and moves the existing makeMultiChannel class method from SimpleDRAM to the support scripts.
The se/fs.py example scripts are updated to make use of the new feature.
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#
9835:cc7a7fc71c42 |
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19-Aug-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
mem: Change AbstractMemory defaults to match the common case
This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change.
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#
9827:f47274776aa0 |
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19-Aug-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
power: Add voltage domains to the clock domains
This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set.
A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain.
The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic.
The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs.
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#
9826:014ff1fbff6d |
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19-Aug-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Move the memory instantiation outside FSConfig
This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions.
The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1.
Going forward, options will be added to support the addition of multi-channel memory controllers.
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#
9793:6e6cefc1db1f |
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27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
sim: Add the notion of clock domains to all ClockedObjects
This patch adds the notion of source- and derived-clock domains to the ClockedObjects. As such, all clock information is moved to the clock domain, and the ClockedObjects are grouped into domains.
The clock domains are either source domains, with a specific clock period, or derived domains that have a parent domain and a divider (potentially chained). For piece of logic that runs at a derived clock (a ratio of the clock its parent is running at) the necessary derived clock domain is created from its corresponding parent clock domain. For now, the derived clock domain only supports a divider, thus ensuring a lower speed compared to its parent. Multiplier functionality implies a PLL logic that has not been modelled yet (create a separate clock instead).
The clock domains should be used as a mechanism to provide a controllable clock source that affects clock for every clocked object lying beneath it. The clock of the domain can (in a future patch) be controlled by a handler responsible for dynamic frequency scaling of the respective clock domains.
All the config scripts have been retro-fitted with clock domains. For the System a default SrcClockDomain is created. For CPUs that run at a different speed than the system, there is a seperate clock domain created. This domain incorporates the CPU and the associated caches. As before, Ruby runs under its own clock domain.
The clock period of all domains are pre-computed, such that no virtual functions or multiplications are needed when calling clockPeriod. Instead, the clock period is pre-computed when any changes occur. For this to be possible, each clock domain tracks its children.
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9790:ccc428657233 |
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27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
config: Add a system clock command-line option
This patch adds a 'sys_clock' command-line option and use it to assign clocks to the system during instantiation.
As part of this change, the default clock in the System class is removed and whenever a system is instantiated a system clock value must be set. A default value is provided for the command-line option.
The configs and tests are updated accordingly.
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9789:233420718e61 |
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27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
config: Add a CPU clock command-line option
This patch adds a 'cpu_clock' command-line option and uses the value to assign clocks to components running at the CPU speed (L1 and L2 including the L2-bus). The configuration scripts are updated accordingly.
The 'clock' option is left unchanged in this patch as it is still used by a number of components. In follow-on patches the latter will be disambiguated further.
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9788:5558ee8dd7d9 |
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27-Jun-2013 |
Akash Bagdia <akash.bagdia@arm.com> |
config: Remove redundant explicit setting of default clocks
This patch removes the explicit setting of the clock period for certain instances of CoherentBus, NonCoherentBus and IOCache where the specified clock is same as the default value of the system clock. As all the values used are the defaults, there are no performance changes. There are similar cases where the toL2Bus is set to use the parent CPU clock which is already the default behaviour.
The main motivation for these simplifications is to ease the introduction of clock domains.
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#
9665:6dbdeee787cc |
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22-Apr-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Add a mem-type config option to se/fs scripts
This patch enables selection of the memory controller class through a mem-type command-line option. Behind the scenes, this option is treated much like the cpu-type, and a similar framework is used to resolve the valid options, and translate the short-hand description to a valid class.
The regression scripts are updated with a hardcoded memory class for the moment. The best solution going forward is probably to get the memory out of the makeSystem functions, but Ruby complicates things as it does not connect the memory controller to the membus.
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9653:5307d06e1d0e |
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22-Apr-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
config: Add a KVM VM to systems with KVM CPUs
KVM-based CPUs need a KVM VM object in the system to manage system-global KVM stuff (VM creation, interrupt delivery, memory managment, etc.). This changeset adds a VM to the system if KVM has been enabled at compile time (the BaseKvmCPU object exists) and a KVM-based CPU has been selected at runtime.
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#
9539:0ac00d9a8aaf |
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15-Feb-2013 |
Anthony Gutierrez <atgutier@umich.edu> |
options: add command line option for dtb file
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9408:10a84dceab25 |
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07-Jan-2013 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Do not use hardcoded physmem in fs script
This patch generalises the address range resolution for the I/O cache and I/O bridge such that they do not assume a single memory. The patch involves adding a parameter to the system which is then defined based on the memories that are to be visible from the I/O subsystem, whether behind a cache or a bridge.
The change is needed to allow interleaved memory controllers in the system.
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9384:877293183bdf |
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07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
arch: Make the ISA class inherit from SimObject
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers.
This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
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#
9317:2daeea4bce1b |
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26-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Add a check for fastmem only used with Atomic CPU
This patch adds an additional check to ensure that the fastmem option is only used if the system is using the Atomic CPU.
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9316:4e2dc4b01c50 |
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26-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
config: Remove unused mem_size in fs.py
This patch removes a segment of dead code that is never used.
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9288:3d6da8559605 |
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15-Oct-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time expressed in Ticks, to a number of cycles that can be scaled with the clock period of the caches. Ultimately this patch serves to enable future work that involves dynamic frequency scaling. As an immediate benefit it also makes it more convenient to specify cache performance without implicitly assuming a specific CPU core operating frequency.
The stat blocked_cycles that actually counter in ticks is now updated to count in cycles.
As the timing is now rounded to the clock edges of the cache, there are some regressions that change. Plenty of them have very minor changes, whereas some regressions with a short run-time are perturbed quite significantly. A follow-on patch updates all the statistics for the regressions.
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9164:d112473185ea |
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22-Aug-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them.
The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split).
As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up.
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#
9129:b57966a6c512 |
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23-Jul-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Config: Use clock option in se/fs script and pass to switch_cpus
This patch changes the se and fs script to use the clock option and not simply set the CPUs clock to 2 GHz. It also makes a minor change to the assignment of the switch_cpus clock to allow different clocks.
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#
9061:135aa8f54bc4 |
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07-Jun-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Config: call to setWorkCountOptions() for all ISAs
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#
9060:ee4104e628f3 |
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07-Jun-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Config: Remove setMipsOptions As status matrix, MIPS fs does not work. Hence, these options are not required. Secondly, the function is setting param values for a CPU class. This seems strange, should probably be done in a different way.
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#
9059:95b525b1d3a0 |
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07-Jun-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Config: changes to a couple of error msgs
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8956:1df031399919 |
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16-Apr-2012 |
Jayneel Gandhi <jayneel@cs.wisc.edu> |
Config: Add command line options for disk image and memory size Added the options to Options.py for FS mode with backward compatibility. It is good to provide an option to specify the disk image and the memory size from command line since a lot of disk images are created to support different benchmark suites as well as per user needs. Change in program also leads to change in memory requirements. These options provide the interface to provide both disk image and memory size from the command line and gives more flexibility.
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8926:570b44fe6e04 |
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03-Apr-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Atomic: Remove the physmem_port and access memory directly
This patch removes the physmem_port from the Atomic CPU and instead uses the system pointer to access the physmem when using the fastmem option. The system already keeps track of the physmem and the valid memory address ranges, and with this patch we merely make use of that existing functionality. As a result of this change, the overloaded getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
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8920:99083b5b7ed4 |
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28-Mar-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Config: Change the way options are added I am not too happy with the way options are added in files se.py and fs.py currently. This patch moves all the options to the file Options.py, functions from which are called when required.
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8919:c1366a30d5eb |
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27-Mar-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
Config: Move setWorkCountOptions() to Simulation.py The function is presently defined in FSConfig.py, which does not seem to be the correct place for it.
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#
8894:351585c17699 |
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09-Mar-2012 |
Ali Saidi <saidi@eecs.umich.edu> |
ARM: Fix memory starting at non-zero address and exceeding max mem for a system.
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#
8887:20ea02da9c53 |
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09-Mar-2012 |
Geoffrey Blake <geoffrey.blake@arm.com> |
CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable
Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes.
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8883:c92153af04ac |
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09-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
cache: Allow main memory to be at disjoint address ranges.
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#
8870:f95c4042f2d0 |
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01-Mar-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for Versatile Express extended memory map
Also clean up how we create boot loader memory a bit.
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#
8863:50ce4deacda9 |
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01-Mar-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: Fix switching of CPUs This patch prevents creation of interrupt controller for cpus that will be switched in later
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8845:a230379caf65 |
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14-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the introduction of the master/slave ports.
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8839:eeb293859255 |
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13-Feb-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Introduce the master/slave port roles in the Python classes
This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves.
The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port.
Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves.
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#
8810:00f0d0230596 |
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01-Feb-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
configs: More fixes for the memory system updates
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8803:f6c5785bc8fd |
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28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of FULL_SYSTEM in the configs directory
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#
8801:1a84c6a81299 |
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28-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make SE vs. FS mode a runtime parameter.
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8723:bbcc7afd82cb |
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25-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Fix fs.py by specifying the range size rather than end
This patch fixes the currently broken fs.py by specifying the size of the bridge range rather than the end address. This effectively subtracts one when determining the address range for the IO bridge (from IO bus to membus), and thus avoids the overlapping ranges.
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8713:2f1a3e335255 |
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17-Jan-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
MEM: Make the bus bridge unidirectional and fixed address range
This patch makes the bus bridge uni-directional and specialises the bus ports to be a master port and a slave port. This greatly simplifies the assumptions on both sides as either port only has to deal with requests or responses. The following patches introduce the notion of master and slave ports, and would not be possible without this split of responsibilities.
In making the bridge unidirectional, the address range mechanism of the bridge is also changed. For the cases where communication is taking place both ways, an additional bridge is needed. This causes issues with the existing mechanism, as the busses cannot determine when to stop iterating the address updates from the two bridges. To avoid this issue, and also greatly simplify the specification, the bridge now has a fixed set of address ranges, specified at creation time.
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#
8661:2d791d07c59b |
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09-Jan-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for running multiple systems
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8659:78f27ef5e919 |
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09-Jan-2012 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Add support for initparam m5 op
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8635:23ba076b2cca |
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01-Dec-2011 |
Chris Emmons <chris.emmons@arm.com> |
VNC: Add support for capturing frame buffer to file each time it is changed.
When a change in the frame buffer from the VNC server is detected, the new frame is stored out to the m5out/frames_*/ directory. Specifiy the flag "--frame-capture" when running configs/example/fs.py to enable this behavior.
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8354:26be660e365a |
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17-Jun-2011 |
Gedare Bloom <gedare@gwmail.gwu.edu> |
ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.
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8061:08e91664adac |
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23-Feb-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Clarifies creation of Linux and baremetal ARM systems.
makeArmSystem creates both bare-metal and Linux systems more cleanly. machine_type was never optional though listed as an optional argument; a system such as "RealView_PBX" must now be explicitly specified. Now that it is a required argument, the placement of the arguments has changed slightly requiring some changes to calls that create ARM systems.
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7925:6823ef6d7a9f |
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07-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86, Config: Move the setting of work count options to a separate function.
This way things that don't care about work count options and/or aren't called by something that has those command line options set up doesn't have to build a fake object to carry in inert values.
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7914:eee5bb0fb8ea |
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07-Feb-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
m5: added work completed monitoring support
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7877:19beb0676222 |
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03-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Mem,X86: Make the IO bridge pass APIC messages back towards the CPU.
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7876:189b9b258779 |
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03-Feb-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Config: Keep track of uncached and cached ports separately.
This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
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#
7861:4ebff121cc0e |
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19-Jan-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Time: Add a mechanism to prevent M5 from running faster than real time.
M5 skips over any simulated time where it doesn't have any work to do. When the simulation is active, the time skipped is short and the work done at any point in time is relatively substantial. If the time between events is long and/or the work to do at each event is small, it's possible for simulated time to pass faster than real time. When running a benchmark that can be good because it means the simulation will finish sooner in real time. When interacting with the real world through, for instance, a serial terminal or bridge to a real network, this can be a problem. Human or network response time could be greatly exagerated from the perspective of the simulation and make simulated events happen "too soon" from an external perspective.
This change adds the capability to force the simulation to run no faster than real time. It does so by scheduling a periodic event that checks to see if its simulated period is shorter than its real period. If it is, it stalls the simulation until they're equal. This is called time syncing.
A future change could add pseudo instructions which turn time syncing on and off from within the simulation. That would allow time syncing to be used for the interactive parts of a session but then turned off when running a benchmark using the m5 utility program inside a script. Time syncing would probably not happen anyway while running a benchmark because there would be plenty of work for M5 to do, but the event overhead could be avoided.
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#
7586:da93206873dc |
|
23-Aug-2010 |
Ali Saidi <Ali.Saidi@arm.com> |
ARM: Add configuration for Linux/Full System
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#
6995:f2b4d8bea5d3 |
|
27-Feb-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Config: Fix fs.py's call to CacheConfig.config_cache.
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#
6981:aba5f7216636 |
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25-Feb-2010 |
Lisa Hsu <Lisa.Hsu@amd.com> |
configs: pull out cache configuration code from se.py and fs.py. Most of these frontend configurations share cache configuration code, pull it out so that changes to caches don't have to require changing multiple config files.
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#
6654:4c84e771cca7 |
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22-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
python: Move more code into m5.util allow SCons to use that code. Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it.
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#
6636:8c68656b8564 |
|
15-Sep-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Add an I/O cache to FS config even if there's just an "L2" cache.
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#
6135:9327451a8e7a |
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26-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86, Config: Make makeX86System consider the number of CPUs, and clean up interrupt assignment.
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#
6122:9af6fb59752f |
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16-Jul-2008 |
Steve Reinhardt <Steve.Reinhardt@amd.com> |
mem: use single BadAddr responder per system. Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
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#
5822:05ffa2c3c800 |
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30-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Errors: Print a URL with a hash of the format string to find more information about an error.
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#
5457:08bd3709d482 |
|
13-Jun-2008 |
Ali Saidi <saidi@eecs.umich.edu> |
Scripts: Check for the appropriate build type as soon as possible.
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#
5299:e61b9f2a9732 |
|
02-Dec-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Move startup code to the system object to initialize a Linux system.
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#
5254:c555f8b07345 |
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15-Nov-2007 |
Korey Sewell <ksewell@umich.edu> |
fix MIPS headers
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#
5222:bb733a878f85 |
|
13-Nov-2007 |
Korey Sewell <ksewell@umich.edu> |
Add in files from merge-bare-iron, get them compiling in FS and SE mode
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#
5142:73aa4932b65b |
|
08-Oct-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Configuration: Move iocache outside of processors loop so it works for MP systems
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#
5133:a88763dd4a84 |
|
07-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Adjust the config scripts for x86 fs.
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#
4968:f1c856d8c460 |
|
08-Aug-2007 |
Vincentius Robby <acolyte@umich.edu> |
Added fastmem option. Lets CPU accesses to physical memory bypass Bus.
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#
4965:ad0e792a5c78 |
|
10-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
DMA: Add IOCache and fix bus bridge to optionally only send requests one way so a cache can handle partial block requests for i/o devices.
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4837:4e5c7f774548 |
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01-Aug-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Configuration: Update the drive systems kernel as well as the testsys kernel with cmd line option.
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4455:18ff8ee46de8 |
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15-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add an l2 cache option to se example config
configs/common/Options.py: configs/example/fs.py: move l2 cache option to Options.py
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4167:ce5d0f62f13b |
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06-Mar-2007 |
Nathan Binkert <binkertn@umich.edu> |
Move all of the parameters of the Root SimObject so they are directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code.
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3970:d54945bab95d |
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03-Jan-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem
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3873:9c1773b9f603 |
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23-Dec-2006 |
Nathan Binkert <binkertn@umich.edu> |
Add options for setting the kernel to run and the script to run
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3819:8a9d3f3d3398 |
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04-Dec-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
automatically build sparc system or alpha system.
configs/example/fs.py: make it an automatic system build for alpha vs. sparc.
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3668:bacb0a392e78 |
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15-Nov-2006 |
Ron Dreslinski <rdreslin@umich.edu> |
Add L2 cache option to fs.py --l2cache
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3514:b166ee5dce91 |
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09-Nov-2006 |
Kevin Lim <ktlim@umich.edu> |
Clean up config scripts to not have to worry about attaching a cache only to the TimingCPU. Now the Atomic CPU works with caches.
configs/common/Simulation.py: Atomic CPU now works properly with caches, so we don't have to do extra parsing to hook up caches only to the timing CPU.
However the O3CPU must always use caches, so a check for that must still exist.
Also change the switch_cpus to be placed at the system level, now that Steve changed how the IntrController gets its CPU. configs/example/fs.py: configs/example/se.py: Atomic CPU now handles caches.
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3481:14362d3b0756 |
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01-Nov-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
factor some more commone code and enable going from checkpoint into arbitrary CPU with or without caches.
configs/common/Simulation.py: enable going from checkpoint into arbitrary CPU with or without caches.
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3476:0e26b5458236 |
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31-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
configs/example/fs.py: configs/example/se.py: src/mem/tport.hh: Hand merge.
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3448:bb2632fa57dc |
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30-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
se.py, fs.py: import Caches Simulation.py: Fix typo - L2Cache --> L1Cache
configs/common/Simulation.py: Fix typo - L2Cache --> L1Cache configs/example/fs.py: configs/example/se.py: import Caches
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3444:6abefa632e10 |
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30-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Use some python os.path stuff to make it more flexible where we can execute this script from.
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3409:769707cf0664 |
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27-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
configs/example/fs.py: configs/example/se.py: hand merge
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3402:db60546818d0 |
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31-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py: configs/example/se.py: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.cc: src/cpu/thread_state.hh: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-atomic.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: No need for mem parameter any more. src/cpu/checker/cpu.cc: Use new constructor for simple thread (no more MemObject parameter). src/cpu/checker/cpu.hh: Remove MemObject parameter. src/cpu/memtest/memtest.hh: Ports now take in their MemObject owner. src/cpu/o3/alpha/cpu_builder.cc: Remove mem parameter. src/cpu/o3/alpha/cpu_impl.hh: Remove memory parameter and clean up handling of TranslatingPort. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/mips/cpu_builder.cc: src/cpu/o3/mips/cpu_impl.hh: src/cpu/o3/params.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_builder.cc: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/simple_params.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/atomic.cc: Remove memory parameter.
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3398:7f14cadf3afd |
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24-Oct-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Fix fs.py. Lisa did you test this? Is there some wierd python version thing?
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3395:49e674f2fb5d |
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27-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
factor out common run code from se.py and fs.py.
configs/example/fs.py: factor out common code. configs/example/se.py: factor out common code
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3394:0a6b4a7a6df6 |
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23-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
warmup of 1B cpu cycles.
configs/example/fs.py: configs/example/se.py: warm up of 1B CPU cycles
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3393:43e1a001a7ce |
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23-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
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3328:50b7be1f9ab6 |
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19-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
First cut at LL/SC support in caches (atomic mode only).
configs/example/fs.py: Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
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3322:bccece90053b |
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23-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
changes regarding fs.py
1) rearrange the options to be in a nice logical order 2) add an option for what i call "standard switch", which is from simple->timing->detailed 3) change the client/server naming system to testsys/drivesys 4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries. 5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
doesn't fully work because of a caching issue, but the python side of things i think should work - the counterpart of se.py does work. i think i should factor out a lot of the common code in both, but i'll do that after this checkin, just to get this in the tree.
configs/example/fs.py: 1) rearrange the options to be in a nice logical order 2) add an option for what i call "standard switch", which is from simple->timing->detailed 3) change the client/server naming system to testsys/drivesys 4) make checkpointing code such that checkpoints taken from the command line override checkpoint instructions compiled into binaries. 5) add an option for maximum number of checkpoints - simulation will stop at max or maxtick, whichever is first
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3314:1247da7b4d26 |
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18-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add --caches option to add caches to server CPUs.
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3312:dbaec4804adf |
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18-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py: Add flag for MP server systems. src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/IntrControl.py: Change CPU from 'any' to 'cpu[0]' to work better with MP sytems. tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-timing-dual.py: Don't need to set console & intrcontrol cpu params anymore (default is fixed now).
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3304:c5917aeb8e2f |
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17-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Rename 'Machine' to 'SysConfig'. Clean up a little.
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3230:e86a03911728 |
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09-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/cpu/simple/timing.hh: tests/configs/o3-timing-mp.py: Hand merge.
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3223:a2b6fa575c05 |
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08-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Clean up configs.
configs/common/FSConfig.py: configs/common/SysPaths.py: configs/example/fs.py: configs/example/se.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: Clean up configs by removing FullO3Config and instead using default values. src/python/m5/objects/FUPool.py: Add in default FUPool. src/python/m5/objects/O3CPU.py: Use defaults better. Also set checker parameters, and fix up a config bug.
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3183:bd8f3870620f |
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09-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N. the default checkpoint directory is the cwd.
so you can restore by a command line like this:
m5.opt fs.py --checkpoint_dir="/my/ckpt/dir" -c 3
configs/example/fs.py: add in checkpoint restoration option, you can restore a checkpoint by giving a directory, and then giving a checkpoint number, the earliest checkpoint is 1, the latest is N.
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3180:664fe611de8e |
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08-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Set cpu_id params (required by ll/sc code now).
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3143:76c70c8bc5c8 |
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06-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
add an option for defining a directory in which to place all your checkpoints. if none, default is cwd.
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3133:ad45cbafebdd |
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05-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
fix the argument to m5.simulate() on a checkpoint.
src/sim/stat_control.cc: add curTick to reset stats printf.
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3088:d8a809416104 |
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29-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add FULL_SYSTEM check to example/fs.py.
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3050:358a23f67bf6 |
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21-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
fs.py: Add temporary cpu.mem parameter settings.
configs/example/fs.py: Add temporary cpu.mem parameter settings.
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3046:fc3297be3869 |
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20-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
configs/example/fs.py: Arg to m5.simulate() is a delta, not an absolute curTick value. I didn't test this change, but I'm not convinced the previous example was tested either, so I don't feel too badly about it.
configs/example/fs.py: Arg to m5.simulate() is a delta, not an absolute curTick value. I didn't test this change, but I'm not convinced the previous example was tested either, so I don't feel too badly about it.
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3025:00fe36086a14 |
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16-Aug-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add etherdump file option
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3022:b3b379cb97ef |
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16-Aug-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
Add in checkpointing in the frontend, so that when a checkpoint is called, the python handles it, and the simulation continues. Also, make it so that the cycle number is part of the cpt dir name, so that multiple checkpoints do not overwrite each other.
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3005:ceb86e85d62d |
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16-Aug-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Finish test clean-up & reorg.
configs/common/FSConfig.py: Add default Machine() param configs/example/fs.py: configs/example/se.py: make it work again src/python/m5/objects/BaseCPU.py: Make mem PhysicalMemory so that a Parent.any proxy works well src/sim/process.cc: Increase default stack size so we don't get an 'increasing stack' message on 'hello world' tests/SConscript: Add full list of current configs. tests/configs/simple-atomic.py: tests/configs/simple-timing.py: don't need SEConfig anymore tests/quick/00.hello/test.py: tests/quick/20.eio-short/test.py: fix tests/run.py: move configs to separate dir
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