fs.py revision 9384:877293183bdf
12929Sktlim@umich.edu# Copyright (c) 2010-2012 ARM Limited 22929Sktlim@umich.edu# All rights reserved. 32932Sktlim@umich.edu# 42929Sktlim@umich.edu# The license below extends only to copyright in the software and shall 52929Sktlim@umich.edu# not be construed as granting a license to any other intellectual 62929Sktlim@umich.edu# property including but not limited to intellectual property relating 72929Sktlim@umich.edu# to a hardware implementation of the functionality of the software 82929Sktlim@umich.edu# licensed hereunder. You may use the software subject to the license 92929Sktlim@umich.edu# terms below provided that you ensure that this notice is replicated 102929Sktlim@umich.edu# unmodified and in its entirety in all distributions of the software, 112929Sktlim@umich.edu# modified or unmodified, in source code or in binary form. 122929Sktlim@umich.edu# 132929Sktlim@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 142929Sktlim@umich.edu# All rights reserved. 152929Sktlim@umich.edu# 162929Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 172929Sktlim@umich.edu# modification, are permitted provided that the following conditions are 182929Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 192929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 202929Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 212929Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 222929Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 232929Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 242929Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 252929Sktlim@umich.edu# this software without specific prior written permission. 262929Sktlim@umich.edu# 272929Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282932Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292932Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302932Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312929Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322929Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332929Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342929Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352929Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362929Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372929Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382929Sktlim@umich.edu# 392929Sktlim@umich.edu# Authors: Ali Saidi 402929Sktlim@umich.edu 412929Sktlim@umich.eduimport optparse 422929Sktlim@umich.eduimport sys 432929Sktlim@umich.edu 442929Sktlim@umich.eduimport m5 452929Sktlim@umich.edufrom m5.defines import buildEnv 462929Sktlim@umich.edufrom m5.objects import * 472929Sktlim@umich.edufrom m5.util import addToPath, fatal 482929Sktlim@umich.edu 492929Sktlim@umich.eduaddToPath('../common') 502929Sktlim@umich.edu 512929Sktlim@umich.edufrom FSConfig import * 522929Sktlim@umich.edufrom SysPaths import * 532929Sktlim@umich.edufrom Benchmarks import * 542929Sktlim@umich.eduimport Simulation 552929Sktlim@umich.eduimport CacheConfig 562929Sktlim@umich.edufrom Caches import * 572929Sktlim@umich.eduimport Options 582929Sktlim@umich.edu 592929Sktlim@umich.eduparser = optparse.OptionParser() 602929Sktlim@umich.eduOptions.addCommonOptions(parser) 612929Sktlim@umich.eduOptions.addFSOptions(parser) 622929Sktlim@umich.edu 632929Sktlim@umich.edu(options, args) = parser.parse_args() 643020Sstever@eecs.umich.edu 653020Sstever@eecs.umich.eduif args: 663020Sstever@eecs.umich.edu print "Error: script doesn't take any positional arguments" 672929Sktlim@umich.edu sys.exit(1) 682929Sktlim@umich.edu 693021Sstever@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of 702929Sktlim@umich.edu# a class, not an instance. 712929Sktlim@umich.eduDriveCPUClass = AtomicSimpleCPU 722929Sktlim@umich.edudrive_mem_mode = 'atomic' 732929Sktlim@umich.edu 742929Sktlim@umich.edu# system under test can be any CPU 752929Sktlim@umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 762929Sktlim@umich.edu 772929Sktlim@umich.eduTestCPUClass.clock = options.clock 782929Sktlim@umich.eduDriveCPUClass.clock = options.clock 792929Sktlim@umich.edu 802929Sktlim@umich.eduif options.benchmark: 812929Sktlim@umich.edu try: 822929Sktlim@umich.edu bm = Benchmarks[options.benchmark] 832929Sktlim@umich.edu except KeyError: 842929Sktlim@umich.edu print "Error benchmark %s has not been defined." % options.benchmark 852929Sktlim@umich.edu print "Valid benchmarks are: %s" % DefinedBenchmarks 862929Sktlim@umich.edu sys.exit(1) 872929Sktlim@umich.eduelse: 882929Sktlim@umich.edu if options.dual: 892929Sktlim@umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 902929Sktlim@umich.edu else: 912929Sktlim@umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 922929Sktlim@umich.edu 932929Sktlim@umich.edunp = options.num_cpus 942929Sktlim@umich.edu 952929Sktlim@umich.eduif buildEnv['TARGET_ISA'] == "alpha": 962929Sktlim@umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 972929Sktlim@umich.eduelif buildEnv['TARGET_ISA'] == "mips": 982929Sktlim@umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 992929Sktlim@umich.eduelif buildEnv['TARGET_ISA'] == "sparc": 1002929Sktlim@umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1012929Sktlim@umich.eduelif buildEnv['TARGET_ISA'] == "x86": 1022929Sktlim@umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1032929Sktlim@umich.eduelif buildEnv['TARGET_ISA'] == "arm": 1042929Sktlim@umich.edu test_sys = makeArmSystem(test_mem_mode, 1054937Sstever@gmail.com options.machine_type, bm[0], 1064937Sstever@gmail.com bare_metal=options.bare_metal) 1074937Sstever@gmail.comelse: 1084937Sstever@gmail.com fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1094937Sstever@gmail.com 1104937Sstever@gmail.comif options.kernel is not None: 1114937Sstever@gmail.com test_sys.kernel = binary(options.kernel) 1124937Sstever@gmail.com 1134937Sstever@gmail.comif options.script is not None: 1144937Sstever@gmail.com test_sys.readfile = options.script 1154937Sstever@gmail.com 1164937Sstever@gmail.comtest_sys.init_param = options.init_param 1174937Sstever@gmail.com 1182929Sktlim@umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 1192929Sktlim@umich.edu 1202929Sktlim@umich.eduif options.caches or options.l2cache: 1212929Sktlim@umich.edu test_sys.iocache = IOCache(clock = '1GHz', 1222929Sktlim@umich.edu addr_ranges=[test_sys.physmem.range]) 1232929Sktlim@umich.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1242929Sktlim@umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1252929Sktlim@umich.eduelse: 1262929Sktlim@umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range]) 1272929Sktlim@umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1284937Sstever@gmail.com test_sys.iobridge.master = test_sys.membus.slave 1294937Sstever@gmail.com 1304937Sstever@gmail.com# Sanity check 1314937Sstever@gmail.comif options.fastmem: 1324937Sstever@gmail.com if TestCPUClass != AtomicSimpleCPU: 1334937Sstever@gmail.com fatal("Fastmem can only be used with atomic CPU!") 1344937Sstever@gmail.com if (options.caches or options.l2cache): 1354937Sstever@gmail.com fatal("You cannot use fastmem in combination with caches!") 1364937Sstever@gmail.com 1374937Sstever@gmail.comfor i in xrange(np): 1384937Sstever@gmail.com if options.fastmem: 1394937Sstever@gmail.com test_sys.cpu[i].fastmem = True 1404937Sstever@gmail.com if options.checker: 1414937Sstever@gmail.com test_sys.cpu[i].addCheckerCpu() 1424937Sstever@gmail.com test_sys.cpu[i].createThreads() 1432929Sktlim@umich.edu 1442929Sktlim@umich.eduCacheConfig.config_cache(options, test_sys) 1452929Sktlim@umich.edu 1462929Sktlim@umich.eduif len(bm) == 2: 1472929Sktlim@umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 1482929Sktlim@umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1492929Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1502929Sktlim@umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1512929Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 1522929Sktlim@umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1532929Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1542929Sktlim@umich.edu drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1552929Sktlim@umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1562929Sktlim@umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 1572929Sktlim@umich.edu 1582929Sktlim@umich.edu drive_sys.cpu = DriveCPUClass(cpu_id=0) 1592997Sstever@eecs.umich.edu drive_sys.cpu.createThreads() 1602997Sstever@eecs.umich.edu drive_sys.cpu.createInterruptController() 1612929Sktlim@umich.edu drive_sys.cpu.connectAllPorts(drive_sys.membus) 1622997Sstever@eecs.umich.edu if options.fastmem: 1632997Sstever@eecs.umich.edu drive_sys.cpu.fastmem = True 1642929Sktlim@umich.edu if options.kernel is not None: 1652997Sstever@eecs.umich.edu drive_sys.kernel = binary(options.kernel) 1662997Sstever@eecs.umich.edu drive_sys.iobridge = Bridge(delay='50ns', 1672997Sstever@eecs.umich.edu ranges = [drive_sys.physmem.range]) 1682929Sktlim@umich.edu drive_sys.iobridge.slave = drive_sys.iobus.master 1692997Sstever@eecs.umich.edu drive_sys.iobridge.master = drive_sys.membus.slave 1702997Sstever@eecs.umich.edu 1712997Sstever@eecs.umich.edu drive_sys.init_param = options.init_param 1722997Sstever@eecs.umich.edu root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 1732997Sstever@eecs.umich.eduelif len(bm) == 1: 1742997Sstever@eecs.umich.edu root = Root(full_system=True, system=test_sys) 1752997Sstever@eecs.umich.eduelse: 1762997Sstever@eecs.umich.edu print "Error I don't know how to create more than 2 systems." 1772997Sstever@eecs.umich.edu sys.exit(1) 1782997Sstever@eecs.umich.edu 1792997Sstever@eecs.umich.eduif options.timesync: 1802997Sstever@eecs.umich.edu root.time_sync_enable = True 1815525Sstever@gmail.com 1825526Sstever@gmail.comif options.frame_capture: 1835525Sstever@gmail.com VncServer.frame_capture = True 1842997Sstever@eecs.umich.edu 1852997Sstever@eecs.umich.eduSimulation.setWorkCountOptions(test_sys, options) 1862997Sstever@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass) 1875525Sstever@gmail.com